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Datasheet Microchip PL123E-05SI

The PL123E-05 (-05H for High Drive) is a high per-formance, low skew, low jitter zero delay buffer designed to distribute high speed clocks

Datasheets

• Скачать » Datasheet PDF, 359 Кб, Файл опубликован: 9 ноя 2015
  PL123E-05 - Low Skew Zero Delay Buffer
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  (Preliminary) PL123E-05 Low Skew Zero Delay Buffer
  FEATURES DESCRIPTION п‚ п‚ п‚ п‚ The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer d esigned
  to distribute high speed clocks. It has five low-skew
  outputs that are synchronized with the input. The sy nchronization is established via CLKOUT feed back to
  the input of the PLL. Since the skew between the input
  and output is less than п‚±100ps, the device acts as a
  zero delay buffer. The input output propagation delay
  can be advanced or delayed by adjusting the load on
  the CLKOUT pin. п‚ п‚ Frequency Range 10MHz to 220MHz
  Zero input -output delay.
  Low output-to-output skew.
  Optional Drive Strength:
  Standard (8mA) PL123E-05
  High (12mA)
  PL123E-05H
  2.5V or 3.3V, В±10% operation.
  Available in 8-pin SOP packaging. These parts are not intended for 5V input-tolerant applications. PIN CONFIGURATION
  REF 1 8 CLKOUT CLK2 2 7 CLK4 CLK1 3 6 VDD GND 4 5 CLK3 SOP-8L
  BLOCK DIAGRAM REF PLL CLKOUT
  CLK1
  CLK2
  CLK3
  CLK4 Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 12/13/11 Page 1 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer ...
• Скачать » Datasheet PDF, 388 Кб, Файл опубликован: 9 ноя 2015
  PL123E-09 - Low Skew Zero Delay Buffer
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  PL123E-09 (Preliminary) Low Skew Zero Delay Buffer
  FEATURES DESCRIPTION п‚ п‚ п‚ п‚ The PL123E-09 (-09H for High Drive) is a high performance, low skew, low jitter zero delay buffer d esigned
  to distribute high speed clocks. It has two low-skew
  output banks, of 4 outputs each, that are synchronized
  with the input. Control of the two banks o f outputs is
  achieved by using the S1 and S2 inputs as shown in
  the Selector Definition table on page 2. п‚ п‚ Frequency Range 10MHz to 220MHz
  Zero input -output delay.
  Low Output to Output Skew
  Optional Drive Strength:
  Standard (8mA) PL123E-09
  High (12mA) PL123E-09H
  2.5V or 3.3V, В±10% operation.
  Available in 16-Pin SOP or TSSOP packages The synchronization is established via CLKOUT feed
  back to the input of the PLL. Since the skew between
  the input and output is less than п‚±100ps, the device
  acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the
  load on the CLKOUT pin.
  These parts are not intended for 5V input-tolerant applications. BLOCK DIAGRAM PLL REF Mux CLKOUT CLKA2
  CLKA3 Bank A CLKA1 CLKA4 S2 Selector
  Inputs CLKB2
  CLKB3 Bank B S1 CLKB1 REF 1 16 CLKOUT CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 VDD 4 13 VDD GND 5 12 GND CLKB1 6 11 CLKB4 CLKB2 7 10 CLKB3 S2 8 9 S1 CLKB4 Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 12/13/11 Page 1 (Preliminary) PL123E-09 Low Skew Zero Delay Buffer
  PIN DESCRIPTIONS ...
• Скачать » Datasheet PDF, 388 Кб, Файл опубликован: 9 ноя 2015
  PL123S-05/-09 - Spread-Compatible Low Skew Zero Delay Buffer
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  PL123S-05/-09
  Spread-Compatible Low Skew Zero Delay Buffer
  FEATURES DESCRIPTION п‚ п‚ The PL123S-05/-09 (-05H/-09H for High Drive) are high
  performance, low skew, low jitter zero delay buffers
  designed to distribute high speed clocks. They have
  one (PL123S-05) or two (PL123S-09) low-skew output
  banks, of 4 outputs each, that are synchronized with
  the input. The PL123S-09 allows control of the banks
  of outputs by using the S1 and S2 inputs as shown in
  the Selector Definition table on page 2. п‚ п‚ п‚ п‚ п‚ п‚ Frequency Range 10MHz to 134 MHz
  Output Options:
  o 5 outputs PL123S-05
  o 9 outputs PL123S-09
  Zero input -output delay
  Optional Drive Strength:
  Standard (8mA) PL123S-05/-09
  High (12mA) PL123S-05H/-09H
  3.3V, В±10% operation
  Available in Commercial and Industrial temperature
  ranges
  Available in 16-Pin SOP or TSSOP (PL123S-09),
  and 8-Pin SOP (PL123S-05) packages
  Spread-compatible with spread-spectrum modulation clock inputs The synchronization is established via CLKOUT feed ...

Цены

Статус

Корпус / Упаковка / Маркировка

Параметры

Экологический статус

Другие варианты исполнения

PL123E-09 PL123S-05 PL123S-09

Модельный ряд

• PL123E-05HSI PL123E-05SC PL123E-05SC-R PL123E-05SI

Классификация производителя

• Clock and Timing > Clock and Data Distribution > Zero Delay Buffers PCIe Buffers

Варианты написания:

PL123E05SI, PL123E 05SI

На английском языке: Datasheet Microchip PL123E-05SI

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