Datasheet Microchip KSZ8842-PMQLI

KSZ8842-16/32
MQL/MVL/MVLI/MBL
2-Port Ethernet Switch with Non-PCI Interface
Data Sheet Rev 1.9 General Description
The KSZ8842-series of 2-port switches includes PCI and
non-PCI CPU interfaces, and are available in 8/16-bit
and 32-bit bus designs (see Ordering Information).
This datasheet describes the KSZ8842M-series of nonPCI CPU interface chips. For information on the
KSZ8842 PCI CPU interface switches, refer to the
KSZ8842P datasheet.
The KSZ8842M is the industry’s first fully managed, 2port switch with a non-PCI CPU interface. It is based on
th
a proven, 4 generation, integrated Layer-2 switch,
compliant with IEEE 802.3u standards. Also an industrial
temperature grade version of the KSZ8842, the
KSZ8842MVLI, can be ordered (see Ordering
Information).
The KSZ8842M can be configured as a switch or as a
low-latency (≤ 310 nanoseconds) repeater in latencycritical, embedded or industrial Ethernet applications.
For industrial applications, the KSZ8842M can run in
half-duplex mode regardless of the application. В® LinkMD The KSZ8842M offers an extensive feature set that
includes tag/port-based VLAN, quality of service (QoS)
priority management, management information base …

KSZ8842-PMQL/PMBL
2-Port Ethernet Switch with PCI Interface
Rev.1.5 General Description
The KSZ8842-series of 2-port switches includes PCI and
non-PCI CPU interfaces. This datasheet describes the
KSZ8842-PMQL/PMBL PCI CPU interface chips.
KSZ8842-PMQL is PQFP package chip, KSZ8842-PMBL
is LFBGA package chip. For information on the
KSZ8842-MQL/MBL CPU non-PCI interface switches,
refer to the KSZ8842-MQL/MBL datasheet.
The KSZ8842-PMQL/PMBL is the industry’s first fully
managed 2-port switch with a 32 bit/33MHz PCI
processor interface. It is a proven, 4th generation,
integrated Layer 2 switch that is compliant with the IEEE
802.3u standard. An industrial temperature grade version
of the KSZ8842-PMQL/PMBL, also can be ordered the
KSZ8842-PMQLI/PMBL AM.
The KSZ8842-PMQL/PMBL can be configured as a
switch or as a low-latency (
1 = Loop back at PMD/PMA of port 2’s PHY
End: TXP2/TXM2 (port 2)
0 = normal operation. P2PHYCTRL,
bit 1 8–0 0 RO VCT fault count …