Datasheet Microchip KSZ8895RQXC — Даташит

KSZ8895MLUB
Integrated 5-Port 10/100 Managed Switch
Revision 2.1 General Description
The KSZ8895MLUB is a highly-integrated Layer 2managed 5-port switch with an optimized design and
plentiful features, qualified to meet AEC-Q100 standard
for automotive applications. It is designed for costsensitive 10/100Mbps 5-port switch systems with on-chip
termination, lowest power consumption and internal core
power controller. These features will save more system
cost. It has 1.4Gbps high-performance memory
bandwidth, shared memory based switch fabric with full
non-blocking configuration. It also provides an extensive
feature set such as power management, programmable
rate limit and priority ratio, tag/port-based VLAN, packets
filtering,
quality-of-service
(QoS)
four-queue
prioritization, management interface, and MIB counters.
Port 5 is a MAC 5 MII interface with PHY mode as
default at switch side. The SW5-MII interface can be
connected to a processor with a MAC MII interface. The KSZ8895MLUB consists of 10/100 PHYs with
patented and enhanced mixed-signal technology, media
access control (MAC) units, a high-speed non-blocking …

KSZ8895MQX/RQX/FQX/MLX
Integrated 5-Port 10/100 Managed Ethernet
Switch with MII/RMII Interface
Features
Advanced Switch Features IEEE 802.1q VLAN Support for up to 128 Active
VLAN Groups (Full-Range 4096 of VLAN IDs) Static MAC Table Supports up to 32 Entries VLAN ID Tag/Untagged Options, Per Port Basis IEEE 802.1p/q Tag Insertion or Removal on a Per
Port Basis Based on Ingress Port (Egress) Programmable Rate Limiting at the Ingress and
Egress on a Per Port Basis Jitter-Free Per Packet Based Rate Limiting Support Broadcast Storm Protection with Percentage Control (Global and Per Port Basis) IEEE 802.1d Rapid Spanning Tree Protocol RSTP
Support Tail Tag Mode (1 Byte Added Before FCS) Support at Port 5 to Inform the Processor Which
Ingress Port Receives the Packet 1.4 Gbps High-Performance Memory Bandwidth
and Shared Memory Based Switch Fabric with
Fully Non-Blocking Configuration Dual MII with MAC 5 and PHY 5 on Port 5, SW5MII/RMII for MAC 5 and P5-MII/RMII for PHY 5 Enable/Disable Option for Huge Frame Size up to
2000 Bytes Per Frame IGMP v1/v2 Snooping (IPv4) Support for Multicast
Packet Filtering IPv4/IPv6 QoS Support Support Unknown Unicast/Multicast Address and
Unknown VID Packet Filtering Self-Address Filtering
Comprehensive Configuration Register Access Serial Management Interface (MDC/MDIO) to All
PHYs Registers and SMI Interface (MDC/MDIO)
to All Registers High-Speed SPI (up to 25 MHz) and I2C Master
Interface to all Internal Registers I/O Pins Strapping and EEPROM to Program
Selective Registers in Unmanaged Switch Mode Control Registers Configurable on the Fly (PortPriority, 802.1p/d/q, AN…)
QoS/CoS Packet Prioritization Support Per Port, 802.1p and DiffServ-Based 1/2/4-Queue QoS Prioritization Selection
пѓЈ 2016 Microchip Technology Inc. Programmable Weighted Fair Queuing for Ratio
Control Re-Mapping of 802.1p Priority Field Per Port …