Datasheet Toshiba TMPM4G9F15FG — Даташит

TMPM4G Group(1)
Datasheet
CMOS Digital Integrated Circuit Silicon Monolithic
LQFP176(20x20mm, 0.4mm pitch) TMPM4G Group(1) LQFP144(20x20mm, 0.5mm pitch)
LQFP128(14x14mm, 0.4mm pitch)
LQFP100(14x14mm, 0.5mm pitch) General Description VFBGA177(13x13mm, 0.8mm pitch)
VFBGA145(12x12mm, 0.8mm pitch) ● Arm ® Cortex®-M4( with FPU) ● Frequency: 1 to 160 MHz, Operation voltage: 2.7 to 3.6 V ● Code Flash: 512 KB to 1536 KB. Data Flash: 32KB ● Built-in High speed 12-bit AD converter and plenty of timers/serial channels Applications
TMPM4G group(1) integrates widely used for the equipment in which high speed data procedure is
required, such as OA/digital products, industrial equipment, and others. Features
● Arm Cortex-M4( with FPU)
‒ Operation frequency: 1 to 160 MHz ● I/O ports: 87 to 155 (Input: 4, Output: 1) ‒ Memory Protection Unit (MPU) ‒ Enable to select Pull-up/Pull-down resistor, Open-drain ● Supply voltage and power consumption
‒ Operation voltage: ‒ 5V tolerant, 3V tolerant 2.7 to 3.6 V ● On-chip debug (JTAG/SW) and NBDIF (RAM monitor) ‒ Low-power consumption operation: IDLE, STOP1, and STOP2 ● Trigger Selector (TRGSEL) ● Operation temperature: ‒ Expand trigger requests for DMA Controller, Timer counter, and -40 to +85℃@operation frequency 1 to 120 MHz others. -40 to +70℃@operation frequency 1 to 160 MHz ● DMA Controller: 3 units ● Internal memory ‒ MDMAC: 1 unit, ‒ Code Flash: 512 KB to 1536 KB, rewritable up to 10,000 times DMA requests: 30 to 32 factors, internal/external triggers ‒ Data Flash: 32 KB, rewritable up to 100,000 times ‒ HDMAC: 2 units, ‒ Data Flash is rewritable during instruction execution DMA requests: 13 to 15 factors, internal/external triggers ‒ RAM: 128 KB to 192 KB and Backup RAM: 2 KB (all products) ● External bus interface(EBIF) ● Clock ‒ Expandable to 64MB(Program/data) ‒ External high speed oscillator: 8 MHz to 20 MHz (Ceramic and ‒ External data bus(separate bug/multiplexed bun): 8/16 bit width Crystal) ‒ Chip select controller: 4 channels ‒ External high speed clock input: 8 to 20 MHz
‒ Internal high speed oscillator1 (IHOSC1):10MHz, user trimming
function
‒ Internal high speed oscillator2 (IHOSC2):10MHz
‒ PLL: 160 MHz output
‒ External low speed oscillator: 32.768 kHz
● Oscillation Frequency Detectior (OFD): Abnormal system clock
detection
● Voltage Detection (LVD): 7 levels. selection between interrupts
and reset outputs
● Interrupt
‒ External: 12 to 16 factors. Integrate digital noise filters (DNF). …