Datasheet Fairchild 74AC169SJ — Даташит

Revised November 1999 74AC169
4-Stage Synchronous Bidirectional Counter
General Description Features The AC169 is fully synchronous 4-stage up/down counter.
The AC169 is a modulo-16 binary counter. It features a
preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the
direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH
transition of the Clock. ■ ICC reduced by 50%
■ Synchronous counting and loading
■ Built-In lookahead carry capability
■ Presettable for programmable operation
■ Outputs source/sink 24 mA Ordering Code:
Order Number Package Number Package Description 74AC169SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC169SJ
74AC169MTC MTC16 74AC169PC N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions
Pin Names
CEP Description
Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input P0–P3 Parallel Data Inputs PE Parallel Enable Input U/D Up-Down Count Control Input Q0–Q3 Flip-Flop Outputs TC Terminal Count Output FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009934 www.fairchildsemi.com 74AC169 4-Stage Synchronous Bidirectional Counter November 1988 74AC169 Functional Description Mode Select Table The AC169 uses edge-triggered J-K-type flip-flops and
have no constraints on changing the control or data input
signals in either state of the Clock. The only requirement is
that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is
LOW, the data on the P0–P3 inputs enters the flip-flops on …