Datasheet Rafael Micro R820T2 — Даташит

O
nl y PRELIMINARY VERSION Fo r安 美 達 R820T
High Performance Low Power
Advanced Digital TV Silicon Tuner
Datasheet CONFIDENTIAL Suite 808, Building 53, No.195, Sec.4, Chung Hsing Road, Chutung, HsinChu 310, Taiwan , R.O.C.
310 台灣新竹縣竹東鎮中興路四段 195 號 53 館 808 室
Tel: 886-3-5820868 Fax: 886-3-5820968 www.rafaelmicro.com © 2011 by Rafael Microelectronics, Inc. All rights reserved. PRELIMINARY VERSION Ordering Information
Part Number Description Package Type R820T Digital TV Silicon Tuner QFN 24 Revision History
Revision Description
Preliminary Release 1.1
1.2 Owner Date Vincent Huang 2011/9/14 Modify reference schematic Vincent Huang 2011/11/16 Modify reference schematic Vincent Huang 2011/11/30 r安 美 達 1.0 O
nl y Contact Information:
Suite 808, Building 53, No. 195, Sec. 4, Chung Hsing Road
Chutung, HsinChu 310,Taiwan, R.O.C.
www.rafaelmicro.com
Tel: 886-3-5820868 Fax: 886-3-5820968
Sales (Taiwan): 886-3-5820868 ext. 211
marshall.lee@rafaelmicro.com
Sales (China): 86-1360-2679953
jaff.wu@rafaelmicro.com
Application Engineering : 886-3-5820868 ext. 235
vincent.huang@rafaelmicro.com © 2011 by Rafael Microelectronics, Inc.
All Rights Reserved. Fo Information in this document is provided in connection with Rafael Microelectronics, Inc. ("Rafael Micro") products. These materials are …

R820T2 Register Description Suite 808, Building 53, No.195, Sec.4, Chung Hsing Road, Chutung, HsinChu 310, Taiwan , R.O.C.
310 台灣新竹縣竹東鎮中興路四段 195 號 53 館 808 室
Tel: 886-3-5820868 CONFIDENTIAL Fax: 886-3-5820968 www.rafaelmicro.com © 2011 by Rafael Microelectronics, Inc. All rights reserved. Programming and Registers 1 1.1 I2C Series Programming Interface
The programmable features of the R820T2 are accessible through an I2C compatible serial interface. Bi-directional
data transfers are programmed through the serial clock (SCL) and serial data lines (SDA) at a standard clock rate of
100 KHz and up to 400KHz. Data Transfer Logic
2 2 The I C control byte includes a fixed 7-bit slave address ID and a read/write (R/W) bit. Fixed I C slave address ID
0011010 (0x1A) is used for default setting. The R/W bit is set 0 for write and 1 for read (Table 1-1). Write mode and
read mode will be further explained in the following sections. I2C Write/Read Address
Table 1-1 : I2C Read / Write Address
2 I C Address(Bin) 2 I C Mode R/W MSB Address (Hex) LSB Write Mode 0 0 1 1 0 1 0 0 0x34 Read Mode 0 0 1 1 0 1 0 1 0x35 CONFIDENTIAL © 2012 by Rafael Microelectronics, Inc. All rights reserved. 2 Write Mode
2 2 When the slave address matches the I C device ID with write control bit , I C start interprets the following first byte
2 as first written register address. These following bytes are all the register data (page write I C control). Register 0 to
2 Register 4 are reserved for internal use only and can be written by I C write command. Figure 1-1 : The Typical Write Mode Sequence
S S Ā {Chip ID,0}
Ex:00110100 A Register
Address :From Master to Slave A A Data
(Reg. Address) A Data
(Reg. Address+1) :Acknowledge (SDA low) S A Data
(Reg. Address+2) :Start P A . A/Ā P :Stop NO Acknowledge (SDA high) Figure 1-2 : An Example of Write Mode Procedure SCL
SDA CONFIDENTIAL © 2012 by Rafael Microelectronics, Inc. All rights reserved. 3 Read Mode 2 When the slave address matches the I C device ID with read control bit, data are immediately transferred after ack
command. Reading data transmission begins from core register 0 to final register until "P"(STOP) occurs. The data
is transmitted from LSB to MSB, and the data of register 0 (0x96) is fixed as reference check point for read mode. Figure 1-3 : The Typical Read Mode Sequence S {Chip ID,0} …