AD746 Figure 10. Open Loop Gain and Figure 11. Settling Time vs. Figure 12. Open Loop Gain vs. Phase Margin vs. Frequency Closed Loop Voltage Gain Supply Voltage Figure 13. Common-Mode and Figure 14. Large Signal Frequency Figure 15. Output Swing and Power Supply Rejection vs. Response Error vs. Settling Time Frequency Figure 16. Total Harmonic Figure 17. Input Noise Voltage Figure 18. Slew Rate vs. Input Distortion vs. Frequency Using Spectral Density Error Signal Circuit of Figure 19 REV. B –5–
