LTC4150 PIN FUNCTIONSSENSE+ (Pin 1): Positive Sense Input. This is the nonin- POL (Pin 6): Battery Current Polarity Open-Drain Output. verting current sense input. Connect SENSE+ to the load POL indicates the most recent battery current polarity when and charger side of the sense resistor. Full-scale current INT is high. A low state indicates the current is fl owing out sense input is 50mV. SENSE+ must be within 60mV of of the battery while high impedance means the current VDD for proper operation. is going into the battery. POL latches its state when INT is asserted low. POL is an open-drain output and can be SENSE– (Pin 2): Negative Sense Input. This is the inverting pulled up to any logic supply up to 9V. In shutdown, POL current sense input. Connect SENSE– to the positive bat- is high impedance. tery terminal side of the sense resistor. Full-scale current sense input is 50mV. SENSE– must be within 60mV of VDD GND (Pin 7): Ground. Connect directly to the negative for proper operation. battery terminal. C +F (Pin 3): Filter Capacitor Positive Input. A capacitor VDD (Pin 8): Positive Power Supply. Connect to the load connected between C + – F and CF fi lters and averages and charger side of the sense resistor. SENSE+ also con- noise and fast battery current variations. A 4.7μF value nects to VDD. VDD operating range is 2.7V to 8.5V. Bypass is recommended. If fi ltering is not desired, leave C + F and VDD with 4.7μF capacitor. C – F unconnected. CLR (Pin 9): Clear Interrupt Digital Input. When asserted C –F (Pin 4): Filter Capacitor Negative Input. A capacitor low for more than 20μs, CLR resets INT high. Charge connected between C + – F and CF fi lters and averages counting is unaffected. INT may be directly connected to noise and fast battery current variations. A 4.7μF value CLR. In this case the LTC4150 will capture each assertion is recommended. If fi ltering is not desired, leave C + F and of INT and wait at least 1μs before resetting it. This ensures C – F unconnected. that INT pulses low for at least 1μs but gives automatic SHDN INT reset. In applications with a logic supply V (Pin 5): Shutdown Digital Input. When asserted low, CC > VDD, SHDN a resistive divider must be used between INT and CLR. forces the LTC4150 into its low current consumption See the Applications Information section. power-down mode and resets the part. In applications with logic supply VCC > VDD, a resistive divider must be INT (Pin 10): Charge Count Interrupt Open-Drain Output. used between SHDN and the logic which drives it. See the INT latches low every 1/(VSENSE • GVF) seconds and is Applications Information section. reset by a low pulse at CLR. INT is an open-drain output and can be pulled up to any logic supply of up to 9V. In shutdown INT is high impedance. 4150fc 5 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM TIMING DIAGRAMS OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
