Datasheet LT1116 (Analog Devices) - 3

LT1116
elecTrical characTerisTics The
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denotes the specifications which apply over full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = –5V, VOUT (Q) = 1.4V, LATCH = 0V. Specifications for VOS, IB, CMRR, and Voltage Gain are valid for single supply operation, V+ = 5V, V– = 0V, unless noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage RS ≤ 100Ω (Note 2) 1.0 ±3.0 mV l 3.5 mV ΔV Input Offset Voltage Drift l 5 µV/°C OS ΔT IOS Input Offset Current (Note 2) l 0.5 2 µA lB Input Bias Current, Sourcing (Note 3) l 10 20 µA Input Voltage Range Arbitrary Supply Range l V– (V+) –2.5 V Single 5V Supply l 0 2.5 V CMRR Common Mode Rejection Ratio –5V ≤ VCM ≤ 2.5V, VS = ±5V l 75 90 dB 0V ≤ VCM ≤ 2.5V l 65 90 dB PSRR Power Supply Rejection Ratio Positive Supply, 4.6V ≤ V+ ≤ 5.4V l 60 75 dB Negative Supply, –7 ≤ V– ≤ –2V l 80 100 dB AV Small Signal Voltage Gain 1V ≤ VOUT ≤ 2V 1400 3000 V/V I+ Positive Supply Current l 27 38 mA I– Negative Supply Current l 5 7 mA VOH Output High Voltage ISOURCE = 1mA l 2.7 3.4 V ISOURCE = 10mA l 2.4 3.0 V VOL Output Low Voltage lSINK = 4mA l 0.3 0.5 V lSINK = 10mA 0.4 V VIH + Positive Latch Threshold l 2.0 V VIL – Latch Threshold l 0.8 V IIL Latch Input Current VLATCH = 0V l –20 –500 µA tPD Propagation Delay ∆VIN = 100mV, OD = 5mV (Note 4) 12 16 ns l 18 ns tPD Propagation Delay ∆VIN = 100mV, OD = 20mV (Note 4) 10 14 ns l 16 ns ∆tPD Differential Propagation Delay ∆VIN = 100mV, OD = 5mV (Note 4) 3 ns tSU Latch Set-Up Time (Note 5) 2 ns tH Latch Hold Time (Note 5) 2 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
tPD and ∆tPD cannot be measured in automatic handling equipment may cause permanent damage to the device. Exposure to any Absolute with low values of overdrive. The LT1116 is sample tested with a 1V step Maximum Rating condition for extended periods may affect device and 500mV overdrive. Correlation tests have shown that tPD and ∆tPD can reliability and lifetime. be guaranteed with this test if additional DC tests are performed to verify
Note 2:
Input offset voltage is defined as the average of two offset internal bias conditions are correct. For low overdrive conditions VOS is voltages measured by forcing first the Q output to 1.4V then forcing added to the measured overdrive. the Q output to 1.4V.
Note 5:
Input latch set-up time, tSU, is the interval in which the input signal
Note 3:
Input bias current is defined as the average of the two input must be stable prior to asserting the latch signal. The hold time, currents. tH, is the interval after the latch is asserted in which the input signal must be stable. 1116fc For more information www.linear.com/LT1116 3