Datasheet LT1394 (Analog Devices) - 3

LT1394
ELECTRICAL CHARACTERISTICS The
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denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25
°
C. V+ = 5V, V– = – 5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOL Output Voltage Swing Low IOUT = – 4mA ● 0.3 0.5 V IOUT = – 10mA 0.4 V I+ Positive Supply Current 6 8.5 mA ● 10.0 mA I– Negative Supply Current 1.2 2.2 mA ● 2.5 mA VIH LATCH Pin High Input Voltage ● 2 V VIL LATCH Pin Low Input Voltage ● 0.8 V IIL LATCH Pin Current VLATCH = 0V ● – 4 – 10 µA tPD Propagation Delay (Note 7) ∆VIN = 100mV, VOD = 5mV 7 9 ns ● 14 ns ∆tPD Differential Propagation Delay (Note 7) ∆VIN = 100mV, VOD = 5mV 0.5 2.2 ns tLPD Latch Propagation Delay (Note 8) 6 ns tSU Latch Setup Time (Note 8) – 0.4 ns tH Latch Hold Time (Note 8) 2 ns tPW(D) Minimum Disable Pulse Width 3 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 7:
tPD and ∆tPD cannot be measured in automatic handling of a device may be impaired. equipment with low values of overdrive. The LT1394 is 100% tested with a
Note 2:
This parameter is guaranteed to meet specified perforamnce 100mV step and 20mV overdrive. Correlation tests have shown that tPD through design and characterization. It has not been tested. and ∆tPD limits can be guaranteed with this test, if additional DC tests are
Note 3:
The LT1394CMS8 and LT1394CS8 are guaranteed to meet performed to guarantee that all internal bias conditions are correct. specified performance from 0°C to 70°C and are designed, characterized Propagation delay (tPD) is measured with the overdrive added to the actual and expected to meet these extended temperature limits, but are not tested VOS. Differential propagation delay is defined as: at – 40°C and 85°C. The LT1394IS8 is guaranteed to meet the extended ∆t PD = tPDLH – tPDHL temperature limits.
Note 8:
Latch propagation delay (tLPD) is the delay time for the output to
Note 4:
Input offset voltage (VOS) is defined as the average of the two respond when the LATCH pin is deasserted. Latch setup time (tSU) is the voltages measured by forcing first one output, then the other to 1.4V. interval in which the input signal must remain stable prior to asserting the
Note 5:
Input bias current (I latch signal. Latch hold time (t B) is defined as the average of the two input H) is the interval after the latch is asserted in currents. which the input signal must remain stable.
Note 6:
Input voltage range is guaranteed in part by CMRR testing and in part by design and characterization. 3