Datasheet MCP6241, MCP6241R, MCP6241U, MCP62412, MCP62414 (Microchip) - 5

MCP6241/1R/1U/2/4 2.0 TYPICAL PERFORMANCE CURVES Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
20% s 90 e 18% 630 Samples nc V 16% CM = VSS ) rre B 85 u 14% PSRR (V c (d CM = VSS) c 12% R O R 10% S 80 of 8% , P ge R ta 6% R n 75 e 4% CM CMRR (V rc CM = -0.3V to +5.3V, e 2% V P DD = 5.0V) 0% 70 -5 -4 -3 -2 -1 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 Input Offset Voltage (mV) Ambient Temperature (°C) FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
CMRR, PSRR vs. Ambient Temperature.
110 120 0 R 100 L = 10.0 kΩ PSRR- 100 V -30 CM = VDD/2 °) 90 B) Gain B) d ( ( 80 -60 e (d 80 CMRR in as a h RR 70 PSRR+ 60 G -90 P M Phase p 60 o , C 40 -120 o -Loop -L RR 50 n S 20 e -150 en P 40 p p O 0 -180 O 30 20 -20 -210 10 100 1k 10k 100k 0.1 1 10 100 1k 10k 100k 1M 10M 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ Frequency (Hz) 01 00 01 02 Freq 03 uency 04 (Hz) 05 06 07 FIGURE 2-2:
PSRR, CMRR vs.
FIGURE 2-5:
Open-Loop Gain, Phase vs. Frequency. Frequency.
25% s 30% s e 180 Samples e 180 Samples nc V nc 20% CM = VDD/2 25% VCM = VDD/2 rre T rre u A = +85°C u TA = +125°C c c 20% c 15% c O O 15% of of 10% ge ge 10% ta ta n n e 5% e 5% rc rc e e P P 0% 0% 0 6 0 2 4 6 8 0 2 4 6 8 0 12 18 24 30 36 42 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. Input Bias Current (pA) Input Bias Current (nA) FIGURE 2-3:
Input Bias Current at +85°C.
FIGURE 2-6:
Input Bias Current at +125°C. © 2008 Microchip Technology Inc. DS21882D-page 5 Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: PSRR, CMRR vs. Frequency. FIGURE 2-3: Input Bias Current at +85˚C. FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-5: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-6: Input Bias Current at +125˚C. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: Input Offset Voltage vs. Output Voltage. FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature. FIGURE 2-13: Slew Rate vs. Ambient Temperature. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply (VSS and VDD) 3.4 Exposed Thermal Pad (EP) 4.0 Application infoRmation 4.1 Rail-to-Rail Inputs FIGURE 4-1: The MCP6241/1R/1U/2/4 Show No Phase Reversal. FIGURE 4-2: Simplified Analog Input ESD Structures. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: Summing Amplifier Circuit. FIGURE 4-9: Effect of Parasitic Capacitance at the Input. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 Mindi™ Circuit Designer & Simulator 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information