Datasheet AD8072, AD8073 (Analog Devices) - 10

AD8072/AD8073 Crosstalk Layout Considerations
Crosstalk between internal amplifiers may vary depending on The specified high speed performance of the AD8072 and which amplifier is being driven and how many amplifiers are AD8073 require careful attention to board layout and compo- being driven. This variation typically stems from pin location on nent selection. Proper RF design techniques and low parasitic the package and the internal layout of the IC itself. Table I component selection are mandatory. illustrates the typical crosstalk results for a combination of The PCB should have a ground plane covering all unused portions conditions. of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the
Table I. AD8073JR Crosstalk Table (dB)
area near the input pins to reduce stray capacitance.
Receive Amplifier
Chip capacitors should be used for supply bypassing. One end
AD8073JR
of the capacitor should be connected to the ground plane and
1 2 3
the other within 1/8 inches of each power pin. An additional
1
X –60 –56 large (4.7 µF–10 µF) tantalum electrolytic capacitor should be connected in parallel, but not necessarily as close to the supply
Drive 2
–60 X –60 pins, to provide current for fast large-signal changes at the
Amplifier 3
–54 –60 X device’s output.
All Hostile
–53 –55 –54 The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a
CONDITIONS
minimum. Capacitance variations of less than 1 pF at the invert- V ing input will affect high speed performance. S = ± 5 V RF = 1 kΩ, RL = 150 Ω Stripline design techniques should be used for long signal traces AV = 2 (greater than approximately 1 inch). These should be designed VOUT = 2 V p-p on Drive Amplifier with a characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end. –10– REV. D