Datasheet LTC1043 (Analog Devices) - 5

LTC1043
TEST CIRCUITS Test Circuit 1. Leakage Current Test Test Circuit 2. RON Test
(7, 13, 6, 18) (8, 14, 5, 15) (7, 13, 6, 18) (8, 14, 5, 15) NOTE: TO OPEN SWITCHES, A S1 AND S3 SHOULD BE CONNECTED + V TO V–. TO OPEN S2, S4, IN + 0V TO 10V COSC PIN SHOULD BE (11, 12, 2, 3) (11, 12, 2, 3) TO V+ COSC 100µA to 1mA A LTC1043 • TC01 CURRENT SOURCE LTC1043 • TC02
Test Circuit 3. Oscillator Frequency, fOSC Test Circuit 4. CMRR Test
7 8 VOUT V– (TEST PIN) 2 17 10 11 COSC V+ + 4 16 CAPACITORS ARE + LTC1043 1µF 1µF NOT ELECTROLYTIC 5 12 6 + IV 13 14 LTC1043 • TC03 + V– ≤ VCM ≤ V+ VCM CMRR = 20 LOG ( VOUT ) NOTE: FOR OPTIMUM CMRR, THE COSC SHOULD BE LARGER THAN 0.0047µF, AND THE SAMPLING CAPACITOR ACROSS PINS 11 AND 12 SHOULD BE PLACED OVER A SHIELD TIED TO PIN 10 LTC1043 • TC04
U U W U APPLICATIO S I FOR ATIO Common Mode Rejection Ratio (CMRR)
1/2 LTC1043 The LTC1043, when used as a differential to single-ended 7 8 converter rejects common mode signals and preserves differential voltages (Figure 1). Unlike other techniques, C+ 11 the LTC1043’s CMRR does not degrade with increasing + + V C V C common mode voltage frequency. During the sampling D S D H mode, the impedance of Pins 2, 3 (and 11, 12) should be C– 12 reasonably balanced, otherwise, common mode signals will appear differentially. The value of the CMRR depends 13 14 on the value of the sampling and holding capacitors + V (C CM S, CH) and on the sampling frequency. Since the common mode voltages are not sampled, the common mode signal frequency can well exceed the CS, CH ARE MYLAR OR POLYSTRENE sampling frequency without experiencing aliasing LTC1043 • AI01 phenomena. The CMRR of Figure 1 is measured by
Figure 1. Differential to Single-Ended Converter
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