Datasheet LTC1096, LTC1096L, LTC1098, LTC1098L (Analog Devices) - 8

LTC1096/LTC1096L LTC1098/LTC1098L
AC CHARACTERISTICS LTC1096/LTC1098 The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSMPL Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles fSMPL(MAX) Maximum Sampling Frequency l 16.5 kHz tCONV Conversion Time See Operating Sequence 8 CLK Cycles tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits (Note 9) l 500 1000 ns tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits (Note 9) l 220 800 ns ten Delay Time, CLK↓ to DOUT Enable See Test Circuits (Note 9) l 160 480 ns thDO Time Output Data Remains Valid After CLK↓ CLOAD = 100pF 400 ns tf DOUT Fall Time See Test Circuits (Note 9) l 70 250 ns tr DOUT Rise Time See Test Circuits (Note 9) l 50 150 ns CIN Input Capacitance Analog Inputs On Channel 25 pF Analog Inputs Off Channel 5 pF Digital Input 5 pF
LTC1096L/LTC1098L The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSMPL Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles fSMPL(MAX) Maximum Sampling Frequency l 16.5 kHz tCONV Conversion Time See Operating Sequence 8 CLK Cycles tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits l 500 1000 ns tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits l 220 800 ns ten Delay Time, CLK↓ to DOUT Enable See Test Circuits l 160 480 ns thDO Time Output Data Remains Valid After CLK↓ CLOAD = 100pF 400 ns tf DOUT Fall Time See Test Circuits l 70 250 ns tr DOUT Rise Time See Test Circuits l 50 200 ns CIN Input Capacitance Analog Inputs On Channel 25 pF Analog Inputs Off Channel 5 pF Digital Input 5 pF
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings analog input does not exceed the supply voltage by more than 50mV, the may cause permanent damage to the device. Exposure to any Absolute output code will be correct. To achieve an absolute 0V to 5V input voltage Maximum Rating condition for extended periods may affect device range will therefore require a minimum supply voltage of 4.950V over reliability and lifetime. initial tolerance, temperature variations and loading. For 5.5V < VCC ≤ 9V,
Note 2:
All voltage values are with respect to GND. reference and analog input range cannot exceed 5.55V. If reference and
Note 3:
For the 8-lead PDIP, consult the factory. analog input range are greater than 5.55V, the output code will not be guaranteed to be correct.
Note 4:
Linearity error is specifi ed between the actual and points of the A/D transfer curve.
Note 7:
The supply voltage range for the LTC1096L/LTC1098L is from 2.65V to 4V. The supply voltage range for the LTC1096 is from 3V to 9V,
Note 5:
Total unadjusted error includes offset, full scale, linearity, but the supply voltage range for the LTC1098 is only from 3V to 6V. multiplexer and hold step errors.
Note 8:
Channel leakage current is measured after the channel selection.
Note 6:
Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode
Note 9:
These specifi cations are either correlated from 5V specifi cations or drop below GND or one diode drop above V guaranteed by design. CC. This spec allows 50mV forward bias of either diode. This means that as long as the reference or 10968fc 8