Datasheet LTC1287 (Analog Devices) - 2

LTC1287
W W W U U W U ABSOLUTE AXI U A R TI GS PACKAGE/ORDER I FOR ATIO (Notes 1 and 2)
Supply Voltage (V TOP VIEW ORDER PART CC) to GND .. 12V Voltage CS 1 NUMBER 8 VCC Analog and Reference Inputs .. –0.3V to V +IN 2 7 CLK CC + 0.3V LTC1287BCN8 Digital Inputs .. –0.3V to 12V –IN 3 6 DOUT LTC1287CCN8 Digital Outputs .. –0.3V to V GND 4 5 V CC + 0.3V REF Power Dissipation ... 500mW N8 PACKAGE 8-LEAD PLASTIC DIP Operating Temperature Range .. 0°C to 70°C TJMAX = 100°C, θJA = 130°C/W (N) Storage Temperature Range ... –65°C to 150°C Lead Temperature (Soldering, 10 sec.).. 300°C J8 PACKAGE LTC1287BCJ8 8-LEAD CERAMIC DIP T LTC1287CCJ8 JMAX = 150°C, θJA = 100°C/W (J)
OBSOLETE PACKAGE
Consider N8 Package for Alternate Source Consult LTC Marketing for parts specified with wider operating temperature ranges.
U U W CO VERTER A D ULTIPLEXER CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) LTC1287B LTC1287C PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Offset Error VCC = 2.7V (Note 4) ● ±3.0 ±3.0 LSB Linearity Error (INL) VCC = 2.7V (Notes 4 & 5) ● ±0.5 ±0.5 LSB Gain Error VCC = 2.7V (Note 4) ● ±0.5 ±1.0 LSB Minimum Resolution for Which No ● 12 12 Bits Missing Codes are Guaranteed Analog and REF Input Range (Note 7) – 0.05V to VCC + 0.05V V On Channel Leakage Current (Note 8) On Channel = 3V ● ±1 ±1 µA Off Channel = 0V On Channel = 0V ● ±1 ±1 µA Off Channel = 3V Off Channel Leakage Current (Note 8) On Channel = 3V ● ±1 ±1 µA Off Channel = 0V On Channel = 0V ● ±1 ±1 µA Off Channel = 3V
AC CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) LTC1287B/LTC1287C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fCLK Clock Frequency (Note 6) (Note 9) 0.5 MHz tSMPL Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles tCONV Conversion Time See Operating Sequence 12 CLK Cycles tCYC Total Cycle Time See Operating Sequence (Note 6) 14 CLK+5.0µs Cycles tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits ● 250 450 ns tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits ● 80 160 ns ten Delay Time, CLK↓ to DOUT Enabled See Test Circuits ● 130 250 ns 1287fa 2