LTC1287 WBLOCK ID AGRA 8 7 VCC CLK INPUT SHIFT REGISTER OUTPUT 6 SHIFT DOUT REGISTER 2 +IN SAMPLE ANALOG 3 AND –IN INPUT MUX HOLD COMP 12-BIT SAR 12-BIT CAPACITIVE DAC CONTROL 1 5 4 AND CS TIMING V GND REF LTC1287 BD TEST CIRCUITSOn and Off Channel Leakage CurrentVoltage Waveforms for DOUT Delay Time, tdDO 3V CLK ION 0.45V A ON CHANNEL tdDO IOFF 2.1V A D OFF CHANNEL OUT 0.6V LTC1287 TC03 POLARITY Voltage Waveforms for D LTC1287 TC1 OUT Rise and Fall Times, tr, tfLoad Circuit for t 2.1V dis and ten DOUT 0.6V TEST POINT tr tf LTC1287 TC04 3V t 3k dis WAVEFORM 2, ten DOUT tdis WAVEFORM 1 Voltage Waveforms for tdis 100pF CS 2.1V LTC1287 TC05 Load Circuit for tdDO, tr and tf DOUT 90% WAVEFORM 1 1.5V (SEE NOTE 1) tdis DOUT 3k WAVEFORM 2 10% (SEE NOTE 2) DOUT TEST POINT NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH 100pF THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH LTC1287 TC06 THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. LTC1287 TC02 1287fa 6
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