Datasheet LTC1291 (Analog Devices) - 2

LTC1291
W W W U U W U ABSOLUTE AXI U A R TI GS PACKAGE/ORDER I FOR ATIO (Notes 1 and 2)
Supply Voltage (VCC) to GND.. 12V TOP VIEW ORDER PART Voltage NUMBER CS 1 8 VCC (VREF) Analog Inputs .. –0.3V to VCC + 0.3V CH0 2 7 CLK LTC1291BCN8 Digital Inputs .. –0.3V to 12V CH1 3 6 DOUT LTC1291CCN8 Digital Outputs .. –0.3V to VCC + 0.3V GND 4 5 DIN LTC1291DCN8 Power Dissipation ... 500mW N8 PACKAGE Operating Temperature Range 8-LEAD PLASTIC DIP LTC1291BC, LTC1291CC, TJMAX = 100°C, θJA = 130°C/ W (N8) LTC1291DC .. 0°C to 70°C J8 PACKAGE LTC1291BCJ8 Storage Temperature Range ... –65 8-LEAD CERAMIC DIP °C to 150°C LTC1291CCJ8 Lead Temperature (Soldering, 10 sec)... 300°C TJMAX = 150°C, θJA = 100°C/ W (J8) LTC1291DCJ8
OBSOLETE PACKAGE
Consider N8 Package for Alternate Source Consult LTC Marketing for parts specified with wider operating temperature ranges.
U U W CO VERTER A D ULTIPLEXER CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) LTC1291B LTC1291C LTC1291D PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Offset Error (Note 4) ● ±3.0 ±3.0 ±3.0 LSB Linearity Error (INL) (Note 4 & 5) ● ±0.5 ±0.5 ±0.75 LSB Gain Error (Note 4) ● ±1.0 ±2.0 ±4.0 LSB Minimum Resolution for which No ● 12 12 12 Bits Missing Codes are Guaranteed Analog Input Range (Note 7) – 0.05V to V V CC + 0.05V On Channel Leakage Current On Channel = 5V ● ±1 ±1 ±1 µA (Note 8) Off Channel = 0V On Channel = 0V ● ±1 ±1 ±1 µA Off Channel = 5V Off Channel Lekage Current On Channel = 5V ● ±1 ±1 ±1 µA (Note 8) Off Channel = 0V On Channel = 0V ● ±1 ±1 ±1 µA Off Channel = 5V
AC CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) LTC1291B/LTC1291C/LTC1291D SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fCLK Clock Frequency VCC = 5V (Note 6) (Note 9) 1.0 MHz tSMPL Analog Input Sample Time See Operating Sequence 2.5 CLK Cycles tCONV Conversion Time See Operating Sequence 12 CLK Cycles tCYC Total Cycle Time See Operating Sequence (Note 6) 18 CLK Cycles + 500ns tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits ● 160 300 ns 1291fa 2