LTC1292/LTC1297 WBLOCK ID AGRA 8 7 VCC CLK INPUT SHIFT REGISTER OUTPUT 6 SHIFT DOUT REGISTER 2 +IN SAMPLE ANALOG 3 AND –IN INPUT MUX HOLD COMP 12-BIT SAR 12-BIT CAPACITIVE DAC CONTROL 1 5 4 AND CS TIMING V GND REF LTC1292/7 BD TEST CIRCUITSOn and Off Channel Leakage CurrentVoltage Waveforms for DOUT Delay Time, tdDO 5V CLK I 0.8V ON A ON CHANNEL tdDO IOFF 2.4V DOUT A OFF CHANNEL 0.4V LTC1292/7 TC04 Voltage Waveforms for DOUT Rise and Fall Times, tr, tf POLARITY LTC1292/7 TC01 2.4V Load Circuit for t D dis and ten OUT 0.4V TEST POINT tr tf LTC1292/7 TC05 5V t 3k dis WAVEFORM 2, ten DOUT t Voltage Waveforms for t dis WAVEFORM 1 dis 100pF CS 2.0V LTC1292/7 TC02 Load Circuit for tdDO, tr and tf DOUT 90% WAVEFORM 1 1.4V (SEE NOTE 1) tdis DOUT 3kΩ WAVEFORM 2 10% (SEE NOTE 2) DOUT TEST POINT NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH 100pF THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH LTC1292/7 TC06 THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. LTC1292/7 TC03 12927fb 7
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