Datasheet LTC1416 (Analog Devices) - 6

LTC1416
U U U PI FU CTIO S A + IN (Pin 1):
±2.5V Positive Analog Input.
CONVST (Pin 23):
Conversion Start Signal. This active
A –
low signal starts a conversion on its falling edge.
IN (Pin 2):
±2.5V Negative Analog Input.
V CS (Pin 24):
The Chip Select input must be low for the
REF (Pin 3):
2.5V Reference Output. Bypass to AGND with 1µF. ADC to recognize CONVST and RD inputs. CS also sets the shutdown mode when SHDN goes low. CS and
REFCOMP (Pin 4):
4.06V Reference Output. Bypass to SHDN low select the quick wake-up nap mode. CS high AGND with 22µF tantalum in parallel with 0.1µF and SHDN low select sleep mode. ceramic, or 22µF ceramic.
BUSY (Pin 25):
The BUSY output shows the converter
AGND (Pin 5):
Analog Ground. status. It is low when a conversion is in progress. Data
D13 to D6 (Pins 6 to 13):
Three-State Data Outputs. is valid on the rising edge of BUSY.
DGND (Pin 14):
Digital Ground for Internal Logic. Tie to
VSS (Pin 26):
–5V Negative Supply. Bypass to AGND AGND. with 10µF tantalum in parallel with 0.1µF ceramic, or
D5 to D0 (Pins 15 to 20):
Three-State Data Outputs. 10µF ceramic.
SHDN (Pin 21):
Power Shutdown Input. Low selects
DVDD (Pin 27):
5V Positive Supply. Tie to Pin 28. shutdown. Shutdown mode selected by CS. CS = 0 for
AVDD (Pin 28):
5V Positive Supply. Bypass to AGND nap mode and CS = 1 for sleep mode. with 10µF tantalum in parallel with 0.1µF ceramic, or
RD (Pin 22):
Read Input. This enables the output 10µF ceramic. drivers when CS is low.
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE A + AV IN DD DV C DD SAMPLE A – V IN SS 4k ZEROING SWITCHES VREF 2.5V REF + REF AMP 14-BIT CAPACITIVE DAC COMP – REFCOMP (4.06V) 14 SUCCESSIVE APPROXIMATION • D13 OUTPUT LATCHES • REGISTER • D0 AGND INTERNAL CONTROL LOGIC DGND CLOCK SHDN CONVST RD CS BUSY 1416 BD 6