Datasheet LTC1419 (Analog Devices) - 6

LTC1419
U U U PI FU CTIO S + A CONVST (Pin 23):
Conversion Start Signal. This active
IN (Pin 1):
±2.5V Positive Analog Input. low signal starts a conversion on its falling edge.
– AIN (Pin 2):
±2.5V Negative Analog Input.
CS (Pin 24):
Chip Select. The input must be low for the
VREF (Pin 3):
2.5V Reference Output. Bypass to AGND ADC to recognize CONVST and RD inputs. CS also sets with 1µF. the shutdown mode when SHDN goes low. CS and
REFCOMP (Pin 4):
4.06V Reference Output. Bypass to SHDN low select the quick wake-up nap mode. CS high AGND with 10µF tantalum in parallel with 0.1µF or 10µF and SHDN low select sleep mode. ceramic.
BUSY (Pin 25):
The BUSY output shows the converter
AGND (Pin 5):
Analog Ground. status. It is low when a conversion is in progress. Data
D13 to D6 (Pins 6 to 13):
Three-State Data Outputs. The valid on the rising edge of BUSY. output format is 2’s complement.
VSS (Pin 26):
– 5V Negative Supply. Bypass to AGND
DGND (Pin 14):
Digital Ground for Internal Logic. Tie to with 10µF tantalum in parallel with 0.1µF or 10µF AGND. ceramic.
D5 to D0 (Pins 15 to 20):
Three-State Data Outputs. The
DVDD (Pin 27):
5V Positive Supply. Short to Pin 28. output format is 2’s complement.
AVDD (Pin 28):
5V Positive Supply. Bypass to AGND
SHDN (Pin 21):
Power Shutdown Input. Low selects with 10µF tantalum in parallel with 0.1µF or 10µF shutdown. Shutdown mode selected by CS. CS = 0 for ceramic. nap mode and CS = 1 for sleep mode.
RD (Pin 22):
Read Input. This enables the output drivers when CS is low.
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE +AIN AVDD CSAMPLE – AIN DVDD 2k ZEROING SWITCHES VREF 2.5V REF VSS + REF AMP 14-BIT CAPACITIVE DAC COMP – REFCOMP (4.096V) AGND 14 SUCCESSIVE APPROXIMATION • D13 OUTPUT LATCHES • REGISTER • D0 DGND INTERNAL CONTROL LOGIC CLOCK 1419 BD SHDN CONVST RD CS BUSY 1419fb 6