LTC1741 WBLOCK DIAGRA A + IN FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED INPUT ADC STAGE ADC STAGE ADC STAGE ADC STAGE – S/H A (5 BITS) (4 BITS) (4 BITS) (2 BITS) IN VCM 2.35V REFERENCE 4.7µF RANGE SHIFT REGISTER SELECT AND CORRECTION REFL REFH INTERNAL CLOCK SIGNALS OVDD 0.5V TO REF 5V SENSE BUF OF D11 DIFFERENTIAL INPUT CONTROL LOGIC DIFF OUTPUT LOW JITTER AND REF DRIVERS CLOCK CALIBRATION LOGIC AMP D0 DRIVER CLKOUT 1741 F01 REFLB REFHA REFLA REFHB ENC ENC MSBINV OE OGND 4.7µF 0.1µF 0.1µF 1µF 1µF Figure 1. Functional Block DiagramW UWTI I G DIAGRA N • ANALOG INPUT t3 t t 1 2 t0 ENC t7 t8 DATA (N – 5) DATA (N – 4) DATA DATA (N – 3) DB11 TO DB0 DB11 TO DB0 t6 CLKOUT t4 t5 t10 t9 OE t t 11 12 DATA N DATA DB11 TO DB0, OF AND CLKOUT 1741 TD 1741f 9
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