Datasheet LTC1857, LTC1858, LTC1859 (Analog Devices) - 9

LTC1857/LTC1858/LTC1859
TIMING DIAGRAMS t2 (CONVST to BUSY Delay)
t2
t
2.4V
1 (For Short Pulse Mode)
CONVST t1 CONVST 50% 50% BUSY 0.4V 1859 TD02 1859 TD01
t6 (Delay Time, SCK
↓
to SDO Valid) t7 (Time from Previous Data Remains Valid After SCK
↓
)
t6
t
t
3, t4, t5 (SCK Timing)
7 SCK 0.4V t4 t5 SCK 2.4V SDO 0.4V t 1859 TD03 3 1859 TD04
t t 8 (SDO Valid After RD
↓
) 9 (RD
↓
to SCK Setup Time)
t8 t9 RD 0.4V RD 0.4V Hi-Z 2.4V SCK 2.4V SDO 0.4V 1859 TD05 1959 TD06
t10 (SDI Setup Time Before SCK
↑
) t11 (SDI Hold Time After SCK
↑
)
t10 t11 SCK 2.4V SCK 2.4V 2.4V SDI 2.4V 0.4V SDI 0.4V 1859 TD07 1859 TD08
t12 (SDO Valid Before BUSY
↑
, RD = 0) t13 (BUS Relinquish Time)
t12 t13 BUSY 2.4V 2.4V RD 2.4V 90% Hi-Z SDO B15 SDO 10% 1859 TD10 1859 TD09 185789fb For more information www.linear.com/LTC1857 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter and Multplexer Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Test Circuits Timing Diagrams Operation Applications Information Package Description Revision History Typical Application Related Parts