LTC1860/LTC1861 FuncTional block DiagraM VCC CONV (SDI) SCK PIN NAMES IN PARENTHESES REFER TO LTC1861 CONVERT BIAS AND SERIAL SDO CLK SHUTDOWN PORT DATA IN 12-BITS IN+ (CH0) + 12-BIT SAMPLING DATA OUT IN– ADC – (CH1) 1860/61 BD GND VREF TesT circuiTsLoad Circuit for tdDO, tr, tf, tdis and tenVoltage Waveforms for SDO Rise and Fall Times, tr, tf TEST POINT V SDO OH VOL 3k VCC tdis WAVEFORM 2, ten SDO tr tf 1860 TC04 tdis WAVEFORM 1 20pF 1860 TC01 Voltage Waveforms for tenVoltage Waveforms for tdis CONV CONV VIH SDO 1860 TC03 SDO 90% WAVEFORM 1 ten (SEE NOTE 1) tdis Voltage Waveforms for SDO Delay Times, tdDO and thDO SDO WAVEFORM 2 10% (SEE NOTE 2) NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH SCK THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL VIL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH tdDO THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL thDO 1860 TC05 VOH SDO VOL 1860 TC02 18601fb 10 For more information www.linear.com/LTC1860 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Typical Application Related Parts
