Datasheet LTC2142-14, LTC2141-14, LTC2140-14 (Analog Devices) - 7

LTC2142-14/ LTC2141-14/LTC2140-14
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2142-14 LTC2141-14 LTC2140-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input l 52.7 59 37.1 42 27.9 33 mA Sine Wave Input 53 37.3 28.1 mA IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 4.4 2.7 1.7 mA PDISS Power Dissipation DC Input l 94.9 107 66.8 76 50.2 60 mW Sine Wave Input, OVDD = 1.2V 100.7 70.4 52.6 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode 54.4 38.7 29.5 mA Sine Input, 3.5mA Mode l 55.8 63 40.2 46 30.9 37 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode 34.3 33.9 33.7 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 65.7 75 65.3 75 65.1 75 mA PDISS Power Dissipation Sine Input, 1.75mA Mode 160 131 114 mW Sine Input, 3.5mA Mode l 219 249 190 218 173 202 mW
All Output Modes
PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 10 10 10 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No Increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2142-14 LTC2141-14 LTC2140-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 65 1 40 1 25 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500 ns Duty Cycle Stabilizer On l 2 7.69 500 2 12.5 500 2 20 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500 ns Duty Cycle Stabilizer On l 2 7.69 500 2 12.5 500 2 20 500 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 6 Cycles Double Data Rate Mode 6.5 Cycles 21421014fa 7