Datasheet LTC2145-14, LTC2144-14, LTC2143-14 (Analog Devices) - 7

LTC2145-14/ LTC2144-14/LTC2143-14
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2145-14 LTC2144-14 LTC2143-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input l 105.2 116 82.8 92 62.8 70 mA Sine Wave Input 105.9 83.3 63.2 mA IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 8.5 7.1 5.4 mA PDISS Power Dissipation DC Input l 189 209 149 166 113 126 mW Sine Wave Input, OVDD = 1.2V 201 159 120 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode 107.3 84.7 64.6 mA Sine Input, 3.5mA Mode l 108.7 123 86.1 97 66.1 75 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode 35.1 34.8 34.5 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 66.3 77 66 76 65.7 76 mA PDISS Power Dissipation Sine Input, 1.75mA Mode 256 215 178 mW Sine Input, 3.5mA Mode l 315 360 274 312 237 272 mW
All Output Modes
PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 16 16 16 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2145-14 LTC2144-14 LTC2143-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 125 1 105 1 80 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2 4 500 2 4.76 500 2 6.25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2 4 500 2 4.76 500 2 6.25 500 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 6 Cycles Double Data Rate Mode 6.5 Cycles 21454314fa 7