Datasheet LTC2153-12 (Analog Devices) - 9

LTC2153-12
pin FuncTions SCK (Pin 38):
Serial Interface Clock Input. In serial
LVDS Outputs (DDR LVDS)
programming mode, (PAR/SER = 0V), SCK is the se- The following pins are differential LVDS outputs. The rial interface clock input. In parallel programming mode output current level is programmable. There is an optional (PAR/SER = VDD), SCK controls the sleep mode (see internal 100Ω termination resistor between the pins of Table 2). each LVDS output pair.
CS (Pin 39):
Serial Interface Chip Select Input. In serial
D –/D + to D –/D + (Pins 18/19, 22/23, 24/25,
programming mode, (PAR/SER = 0V), CS is the serial
0_1 0_1 10_11 10_11 28/29, 31/32, 33/34):
Double-Data Rate Digital Outputs. interface chip select input. When CS is low, SCK is enabled Two data bits are multiplexed onto each differential output for shifting data on SDI into the mode control registers. pair. The even data bits (D0, D2, D4, D6, D8, D10) appear In parallel programming mode (PAR/SER = VDD), CS when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, controls the clock duty cycle stabilizer (see Table 2). D9, D11) appear when CLKOUT+ is high.
PAR/SER (Pin 40):
Programming Mode Selection Pin. Connect to ground to enable the serial programming
CLKOUT–, CLKOUT+ (Pins 26, 27):
Data Output Clock. mode. CS, SCK, SDI and SDO become a serial interface The digital outputs normally transition at the same time that control the A/D operating modes. Connect to V as the falling and rising edges of CLKOUT+. The phase of DD to enable the parallel programming mode where CS, SCK and CLKOUT+ can also be delayed relative to the digital outputs SDI become parallel logic inputs that control a reduced by programming the mode control registers. set of the A/D operating modes. PAR/SER should be con-
OF–, OF+ (Pins 14, 15):
Over/Underflow Digital Output. nected directly to ground or the VDD of the part and not OF+ is high when an overflow or underflow has occurred. be driven by a logic signal. This underflow is valid only when CLKOUT+ is low. In the second half clock cycle, the overflow is set to 0.
FuncTional block DiagraM
VDD OVDD D10_11 12-BIT ANALOG CORRECTION • S/H OUTPUT PIPELINED DDR INPUT LOGIC DRIVERS • ADC LVDS • D0_1 VCM V 0.1µF CM OGND BUFFER BUFFER GND CLOCK/DUTY CS CLOCK CYCLE CONTROL SCK SPI SDI VREF SDO 2.2µF PAR/SER 1.25V REFERENCE GND GND RANGE SENSE SELECT 215312 F01
Figure 1. Functional Block Diagram
215312fa For more information www.linear.com/LTC2153-12 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Typical Applications Package Description Related Parts