LTC2162/LTC2161/LTC2160 power requireMenTsThe l denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25°C. (Note 9)LTC2162LTC2161LTC2160SYMBOL PARAMETERCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITS IVDD Analog Supply Current Sine Wave Input 1.75mA Mode 50.3 37.3 26.8 mA 3.5mA Mode l 51.1 57 38.2 42 27.7 31 mA IOVDD Digital Supply Current Sine Wave Input 1.75mA Mode 21.5 21.4 21.1 mA (OVDD = 1.8V) 3.5mA Mode l 41.2 46 41.1 46 40.9 46 mA PDISS Power Dissipation Sine Wave Input, 1.75mA Mode 129 106 86 mW Sine Wave Input, 3.5mA Mode l 166 186 143 159 123 139 mW All Output Modes PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 10 10 10 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No Increase for Nap or Sleep Modes) TiMing characTerisTicsThe l denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25°C. (Note 5)LTC2162LTC2161LTC2160SYMBOL PARAMETERCONDITIONSMINTYPMAXMINTYPMAXMINTYPMAXUNITS fS Sampling Frequency (Note 10) l 1 65 1 40 1 25 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500 ns Duty Cycle Stabilizer On l 2 7.69 500 2 12.5 500 2 20 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500 ns Duty Cycle Stabilizer On l 2 7.69 500 2 12.5 500 2 20 500 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITSDIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 6 Cycles Double Data Rate Mode 6.5 Cycles DIGITAL DATA OUTPUTS (LVDS MODE) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 6.5 Cycles SPI PORT TIMING (Note 8) tSCK SCK Period Write Mode l 40 ns Readback Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns 216210f 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
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