Datasheet LTC2175-12, LTC2174-12, LTC2173-12 (Analog Devices) - 6

LTC2175-12/ LTC2174-12/LTC2173-12
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2175-12 LTC2174-12 LTC2173-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 276 300 218 240 180 196 mA IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode l 27 31 26 31 25 29 mA 2-Lane Mode, 3.5mA Mode l 49 54 48 53 47 52 mA PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode l 545 596 439 488 369 405 mW 2-Lane Mode, 3.5mA Mode l 585 637 479 527 409 446 mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 85 85 85 mW PDIFFCLK Power Increase With Differential Encode Mode Enabled 20 20 20 mW (No Increase for Sleep Mode)
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2175-12 LTC2174-12 LTC2173-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Notes 10,11) l 5 125 5 105 5 80 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 100 4.52 4.76 100 5.93 6.25 100 ns Duty Cycle Stabilizer On l 2 4 100 2 4.76 100 2 6.25 100 ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 100 4.52 4.76 100 5.93 6.25 100 ns Duty Cycle Stabilizer On l 2 4 100 2 4.76 100 2 6.25 100 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 1/(8 • fS) s 2-Lanes, 14-Bit Serialization 1/(7 • fS) s 2-Lanes, 12-Bit Serialization 1/(6 • fS) s 1-Lane, 16-Bit Serialization 1/(16 • fS) s 1-Lane, 14-Bit Serialization 1/(14 • fS) s 1-Lane, 12-Bit Serialization 1/(12 • fS) s tFRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tDATA DATA to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tPD Propagation Delay (Note 8) l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P Pipeline Latency 6 Cycles 21754312fa 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts