Datasheet LTC2185, LTC2184, LTC2183 (Analog Devices) - 7

LTC2185/LTC2184/LTC2183
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2185 LTC2184 LTC2183 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input l 206 228 171 188 111 124 mA Sine Wave Input 209 173 113 mA IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 10 8 6 mA PDISS Power Dissipation DC Input l 370 410 308 339 200 223 mW Sine Wave Input, OVDD = 1.2V 388 321 211 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode 211 175 115 mA Sine Input, 3.5mA Mode l 213 233 177 193 117 128 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode 40 40 39 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 76 86 75 85 75 84 mA PDISS Power Dissipation Sine Input, 1.75mA Mode 452 387 277 mW Sine Input, 3.5mA Mode l 520 574 454 500 346 382 mW
All Output Modes
PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 16 16 16 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No increase for Nap or Sleep Modes)
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2185 LTC2184 LTC2183 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 125 1 105 1 80 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2 4 500 2 4.76 500 2 6.25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2 4 500 2 4.76 500 2 6.25 500 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 6 Cycles Double Data Rate Mode 6.5 Cycles 218543f 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts