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Datasheet LTC2208-14 (Analog Devices) - 6

ПроизводительAnalog Devices
Описание14-Bit, 130Msps ADC
Страниц / Страница28 / 6 — The. POWER REQUIREMENTS. denotes the specifi cations which apply over the …
Формат / Размер файлаPDF / 730 Кб
Язык документаанглийский

The. POWER REQUIREMENTS. denotes the specifi cations which apply over the full operating temperature

The POWER REQUIREMENTS denotes the specifi cations which apply over the full operating temperature

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LTC2208-14
The POWER REQUIREMENTS
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 8) l 3.135 3.3 3.465 V PSHDN Shutdown Power SHDN = VDD 0.2 mW
STANDARD LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 V IVDD Analog Supply Current l 401 470 mA IOVDD Output Supply Voltage l 71 90 mA PDIS Power Dissipation l 1498 1782 mW
LOW POWER LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 V IVDD Analog Supply Current l 401 470 mA IOVDD Output Supply Voltage l 40 50 mA PDIS Power Dissipation l 1356 1650 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 0.5 3.6 V IVDD Analog Supply Current l 401 470 mA PDIS Power Dissipation l 1320 1551 mW
The TIMING CHARACTERISTICS
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) l 1 130 MHz tL ENC Low Time Duty Cycle Stabilizer Off (Note 7) l 3.65 3.846 1000 ns Duty Cycle Stabilizer On (Note 7) l 2.6 3.846 1000 ns tH ENC High Time Duty Cycle Stabilizer Off (Note 7) l 3.65 3.846 1000 ns Duty Cycle Stabilizer On (Note 7) l 2.6 3.846 1000 ns tAP Sample-and-Hold Aperture Delay –1 ns
LVDS OUTPUT MODE (STANDARD AND LOW POWER)
tD ENC to DATA Delay (Note 7) l 1.3 2.5 3.8 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.5 3.8 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 ns tRISE Output Rise Time 0.5 ns tFALL Output Fall Time 0.5 ns Data Latency Data Latency 7 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1.3 2.7 4 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 ns Data Latency Data Latency Full Rate CMOS 7 Cycles Demuxed 7 Cycles 220814fb 6
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