Datasheet LTC2226H (Analog Devices) - 7

LTC2226H
PIN FUNCTIONS GND (Pins 1, 4, 9, 13, 15, 18, 24, 25, 29, 32, 36, 37, OE (Pin 17):
Output Enable Pin. Refer to SHDN pin func-
48):
ADC Power Ground. tion.
AIN+ (Pin 2):
Positive Differential Analog Input.
NC (Pins 19, 20):
Do not connect these pins.
AIN- (Pin 3):
Negative Differential Analog Input.
D0–D11 (Pins 21-23, 26-28, 33-35, 38-40):
Digital Out-
REFH (Pins 5, 6):
ADC High Reference. Bypass to Pins 7, puts. D11 is the MSB. 8 with a 0.1µF ceramic chip capacitor as close to the pin
OGND (Pin 30):
Output Driver Ground. as possible. Also bypass to Pins 7, 8 with an additional
OV
2.2µF ceramic chip capacitor and to GND with a 1µF ce-
DD (Pin 31):
Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. ramic chip capacitor.
OF (Pin 41):
Over/Under Flow Output. High when an over
REFL (Pin 7, 8):
ADC Low Reference. Bypass to Pins 5, 6 or under flow has occurred. with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pin 5, 6 with an additional 2.2µF
MODE (Pin 42):
Output Format and Clock Duty Cycle ceramic chip capacitor and to ground with a 1µF ceramic Stabilizer Selection Pin. Connecting MODE to GND selects chip capacitor. offset binary output format and turns the clock duty cycle stabilizer off. 1/3 V
V
DD selects offset binary output format
DD (Pins 10, 11, 12, 46, 47):
3V Supply. Bypass to GND and turns the clock duty cycle stabilizer on. 2/3 V with 0.1µF ceramic chip capacitors. DD selects 2’s complement output format and turns the clock duty
CLK (Pin 14):
Clock Input. The input sample starts on the cycle stabilizer on. VDD selects 2’s complement output positive edge. format and turns the clock duty cycle stabilizer off.
SHDN (Pin 16):
Shutdown Mode Selection Pin. Connecting
SENSE (Pin 43):
Reference Programming Pin. Connecting SHDN to GND and OE to GND results in normal operation SENSE to VCM selects the internal reference and a ±0.5V with the outputs enabled. Connecting SHDN to GND and input range. VDD selects the internal reference and a ±1V OE to VDD results in normal operation with the outputs at input range. An external reference greater than 0.5V and high impedance. Connecting SHDN to VDD and OE to GND less than 1V applied to SENSE selects an input range of results in nap mode with the outputs at high impedance. ±VSENSE. ±1V is the largest valid input range. Connecting SHDN to VDD and OE to VDD results in sleep
V
mode with the outputs at high impedance.
CM (Pins 44, 45):
1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip If the clock duty cycle stabilizer is used, a >1µs high pulse capacitor. should be applied to the SHDN pin once the power supplies are stable at power up. 2226hfc 7