LTC2226H FUNCTIONAL BLOCK DIAGRAM A + IN INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED SIXTH PIPELINED – S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE AIN VCM 1.5V REFERENCE SHIFT REGISTER 2.2µF AND CORRECTION RANGE SELECT REFH REFL INTERNAL CLOCK SIGNALS OVDD REF SENSE BUF OF D11 DIFF CLOCK/DUTY CONTROL OUTPUT REF CYCLE LOGIC • DRIVERS AMP CONTROL • • D0 REFH 0.1µF REFL 2226H F01 OGND CLK MODE SHDN OE 2.2µF 1µF 1µF Figure 1. Functional Block DiagramTIMING DIAGRAM tAP ANALOG N N + 2 N + 4 INPUT N + 3 N + 5 tH N + 1 tL CLK tD D0-D11, OF N – 5 N – 4 N – 3 N – 2 N – 1 N 2226H TD01 2226hfc 8
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