LTC2258-12 LTC2257-12/LTC2256-12 TiMing DiagraMsFull-Rate CMOS Output Mode TimingAll Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD D0-D11, OF N – 5 N – 4 N – 3 N – 2 N – 1 tC CLKOUT+ CLKOUT– 225812 TD01 Double Data Rate CMOS Output Mode TimingAll Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 ••• D10_11 D10N-5 D11N-5 D10N-4 D11N-4 D10N-3 D11N-3 D10N-2 D11N-2 OF OFN-5 OFN-4 OFN-3 OFN-2 tC tC CLKOUT+ CLKOUT– 225812 TD02 225812fd 8 For more information www.linear.com/LTC2258-12 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
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