LTC2268-12/ LTC2267-12/LTC2266-12 TiMing DiagraMs2-Lane Output Mode, 12-Bit Serialization tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ t t DATA tSER FRAME FR+ FR– tPD tSER OUT#A– D7 D5 D3 D1 D11 D9 D7 D5 D3 D1 D11 D9 D7 OUT#A+ OUT#B– D6 D4 D2 D0 D10 D8 D6 D4 D2 D0 D10 D8 D6 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 226812 TD03 1-Lane Output Mode, 16-Bit Serialization tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– DX* DY* 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* 0 0 D11 D10 D9 D8 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 226812 TD04 OUT#B+, OUT#B– ARE DISABLED *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS. 22687612fa 8 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Digital Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
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