Datasheet LTC2273, LTC2272 (Analog Devices) - 7

LTC2273/LTC2272
TIMING DIAGRAMS
tAP N + 9 N + 2 N + 10 ANALOG INPUT N N + 1 N + 8 tCONV ENC+ tH tL INTERNAL N – 6 N – 5 N – 4 N + 3 N + 4 PARALLEL DATA INTERNAL N – 9 N – 8 N – 7 N N + 1 8B/10B DATA LATP tBIT CMLOUT+/CMLOUT– N – 10 N – 9 N – 8 N – 1 N 22732 TD01
Analog Input to Serial Data Out Timing
tCONV N N + 3 N – 1 N + 2 N + 4 ANALOG INPUT N + 1 N + 5 tHD tSU ENC+ tCS(MIN) SYNC+ tCS(MAX) LATSC CMLOUT+/CMLOUT– N – 10 N – 9 N – 8 N – 7 K28.5 (x2) K28.5 (x2) 22732 TD02
SYNC+ Falling Edge to Comma (K28.5) Timing
tCONV N N + 3 N – 1 N + 2 ANALOG INPUT N + 4 N + 1 tHD tSU ENC+ tCS(MIN) SYNC+ tCS(MAX) LATSD CMLOUT+/CMLOUT– K28.5 (x2) K28.5 (x2) K28.5 (x2) N – 7 N – 6 22732 TD03
SYNC+ Rising Edge to Data Timing
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