Datasheet LTC2452 (Analog Devices) - 9

LTC2452
applicaTions inForMaTion
t3 t t 1 2 CS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDO MSB LSB SCK 2452 F04 tKQ tlSCK thSCK
Figure 4. Data Output Timing
t1 t2 CS SDO SCK = HIGH CONVERT SLEEP 2452 F05
Figure 5. Conversion Status Monitoring Mode
with the most significant bit of the result being present at at approximately 16.6ms (23ms maximum). Therefore, the SDO output pin (SDO = D15) once CS goes low. A new external timing can be used to determine the completion of a data bit appears at the SDO output pin after each falling conversion cycle. edge detected at the SCK input pin. The output data can be reliably latched by the user using the rising edge of SCK.
SERIAL INTERFACE Conversion Status Monitor
The LTC2452 transmits the conversion result and receives the start of conversion command through a synchronous For certain applications, the user may wish to monitor 3-wire interface. This interface can be used during the the LTC2452 conversion status. This can be achieved CONVERT and SLEEP states to assess the conversion by holding SCK HIGH during the conversion cycle. In status and during the DATA OUTPUT state to read the this condition, whenever the CS input pin is pulled low conversion result, and to trigger a new conversion. (CS = LOW), the SDO output pin will provide an indication of the conversion status. SDO = HIGH is an indication of
Serial Interface Operation Modes
a conversion cycle in progress while SDO = LOW is an indication of a completed conversion cycle. An example The modes of operation can be summarized as follows: of such a sequence is shown in Figure 5. 1) The LTC2452 functions with SCK idle high (commonly Conversion status monitoring, while possible, is not re- known as CPOL = 1) or idle low (commonly known as quired for LTC2452 as its conversion time is fixed and equal CPOL = 0). 2452fd For more information www.linear.com/LTC2452 9