LTC2461/LTC2463 APPLICATIONS INFORMATION current by approximately 50%. While in the Nap state, The LTC2461/LTC2463 perform offset calibrations every the reference remains powered up. To power down the conversion cycle. This calibration is transparent to the reference in addition to the converter, the user can select user and has no effect upon the cyclic operation described the SLEEP mode during the DATA INPUT/OUTPUT state. previously. The advantage of continuous calibration is Once the next conversion is complete, SLEEP state is stability of the ADC performance with respect to time and entered and power is reduced to 200nA. The reference temperature. is powered up once a valid read/write is acknowledged. The LTC2461/LTC2463 include a proprietary input sampling The reference startup time is 12ms (if the reference and scheme that reduces the average input current by several compensation capacitor values are both 0.1μF). orders of magnitude when compared to traditional delta- Power-Up Sequence sigma architectures. This allows external filter networks to interface directly to the LTC2461/LTC2463. Since the When the power supply voltage (VCC) applied to the con- average input sampling current is 50nA, an external RC verter is below approximately 2.1V, the ADC performs a lowpass filter using 1kΩ and 0.1µF results in <1LSB power-on reset. This feature guarantees the integrity of additional error. Additionally, there is negligible leakage the conversion result. current between IN+ and IN–. When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for Input Voltage Range (LTC2461) approximately 0.5ms. The POR signal clears all internal Ignoring offset and full-scale errors, the LTC2461 will registers. Following the POR signal, the LTC2461/LTC2463 theoretically output an “all zero” digital result when the start a conversion cycle and follow the succession of states input is at ground (a zero scale input) and an “all one” shown in Figure 2. The reference startup time following a digital result when the input is at VREF (VREFOUT = 1.25V). POR is 12ms (CCOMP = CREFOUT = 0.1μF). The first conver- In an underrange condition, for all input voltages below sion following power-up will be invalid since the reference zero scale, the converter will generate the output code 0. In voltage has not completely settled. The first conversion an overrange condition, for all input voltages greater than following power up can be discarded using the data abort VREF, the converter will generate the output code 65535. command or simply read and ignored. The following con- For applications that require an input range greater than versions are accurate to the device specifications. 0V to 1.25V, please refer to the LTC2451. Ease of UseInput Voltage Range (LTC2463) The LTC2461/LTC2463 data output has no latency, filter As mentioned in the Output Data Format section, the output settling delay or redundant results associated with the code is given as 32768 • (V + – IN – VIN )/VREF + 32768. For conversion cycle. There is a one-to-one correspondence (V + – IN – VIN ) ≥ VREF, the output code is clamped at 65535 between the conversion and the output data. Therefore, (all ones). For (V + – IN – VIN ) ≤ –VREF, the output code is multiplexing multiple analog input voltages requires no clamped at 0 (all zeroes). special actions. The LTC2463 includes a proprietary architecture that can, typically, digitize each input up to 8 LSBs above 24613fa 8 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Applications Information Package Description Electrical Characteristics Analog Inputs Power Requirements I2c Inputs and Outputs I2c Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts
