Datasheet LT3012 (Analog Devices) - 15

LT3012
PACKAGE DESCRIPTION DE Package 12-Lead Plastic DFN (4mm
×
3mm)
(Reference LTC DWG # 05-08-1695) 4.00 ±0.10 R = 0.115 0.40 ± 0.10 (2 SIDES) TYP 7 12 0.70 ±0.05 R = 0.05 TYP 3.30 ±0.05 3.30 ±0.10 3.60 ±0.05 3.00 ±0.10 2.20 ±0.05 1.70 ± 0.05 (2 SIDES) 1.70 ± 0.10 PIN 1 PIN 1 NOTCH TOP MARK R = 0.20 OR PACKAGE (NOTE 6) 0.35 × 45° OUTLINE CHAMFER 6 1 (UE12/DE12) DFN 0806 REV D 0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 BSC 0.50 BSC 2.50 REF 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
FE Package 16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
4.90 – 5.10* (.193 – .201) 3.58 (.141) 3.58 (.141) 16 1514 13 12 10 11 9 6.60 ±0.10 2.94 4.50 ±0.10 (.116) SEE NOTE 4 2.94 6.40 (.116) (.252) 0.45 ±0.05 BSC 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 RECOMMENDED SOLDER PAD LAYOUT 1.10 4.30 – 4.50* (.0433) 0.25 (.169 – .177) MAX REF 0° – 8° 0.65 0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15 (.0035 – .0079) (.020 – .030) BSC (.002 – .006) 0.195 – 0.30 FE16 (BB) TSSOP 0204 (.0077 – .0118) TYP NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE MILLIMETERS FOR EXPOSED PAD ATTACHMENT 2. DIMENSIONS ARE IN (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3. DRAWING NOT TO SCALE 3012fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15