Datasheet LT1308A, LT1308B (Analog Devices) - 10

LT1308A/LT1308B
APPLICATIONS INFORMATION
LBI LBO A SEPIC (Single-Ended Primary Inductance Converter) GROUND PLANE schematic is shown in Figure 8. This converter topology C1 produces a regulated output over an input voltage range + VIN that spans (i.e., can be higher or lower than) the output. Recommended component placement for an SO-8 package SEPIC is shown in Figure 9. R1 1 14 C2 2 13 R2 L1 4.7μF L1A CERAMIC SHUTDOWN 3 12 CTX10-2 D1 VIN 3V TO 4 LT1308A 11 10V LT1308B V 5 10 IN SW + MULTIPLE C1 L1B VIAs 6 9 47μF LT1308B R1 309k VOUT 7 8 SHUTDOWN SHDN FB 5V 500mA VC GND + R2 D1 47k + 100k C3 220μF C2 GND 680pF 6.3V VOUT C1: AVX TAJC476M016 D1: IR 10BQ015 C2: TAIYO YUDEN EMK325BJ475(X5R) L1: COILTRONICS CTX10-2 1308A/B F08 C3: AVX TPSD227M006 1308 F07
Figure 7. Recommended Component Figure 8. SEPIC (Single-Ended Primary Placement for TSSOP Boost Converter. Inductance Converter) Converts 3V to 10V Placement is Similar to Figure 4 Input to a 5V/500mA Regulated Output
LBI LBO GROUND PLANE C1 + VIN R1 1 8 2 7 LT1308A R2 LT1308B SHUTDOWN 3 6 L1A L1B 4 5 MULTIPLE C3 C2 VIAs + GND D1 VOUT 1308 F09
Figure 9. Recommended Component Placement for SEPIC
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