LT1533 WBLOCK DIAGRA SHDN VIN PGND COL A COL B VC LDO REGULATOR + NEGATIVE OUTPUT FEEDBACK DRIVERS INTERNAL VCC – AMP + 100k 50k NFB – – RVSL SLEW CONTROL – FB R COMP CSL gm + ERROR + AMP + S Q 1.25V FF R RT OSCILLATOR CT T Q SYNC FF BK QB GND DUTY 1533 BD UOPERATIO In noise sensitive applications, switching regulators tend ply components that can create conducted and radiated to be ruled out as a power supply option due to their electromagnetic interference. The current mode control propensity for generating unwanted noise. When switch- provides excellent AC and DC line regulation and simplifies ing supplies are required due to efficiency or input/output loop compensation. voltage constraints, great pains must be taken to work around the noise generated by a typical supply. These Current Mode Control steps may include precise synchronization of the power A switching cycle begins with an oscillator discharge pulse supply oscillator to an external clock, synchronizing the which resets the RS flip-flop, turning on one of the output rest of the circuit to the power supply oscillator, or halting drivers (refer to Block Diagram). The switch current is power supply switching during noise sensitive operations. sensed across an internal resistor and the resulting volt- The LT1533 greatly simplifies the task of eliminating age is amplified and compared to the output of the error supply noise by enabling the design of an inherently low amplifier (VC pin). The driver is turned off once the output noise switching regulator power supply. of the current sense amplifier exceeds the voltage on the The LT1533 is a fixed frequency, current mode switching VC pin. The toggle flip-flop ensures that the two output regulator with unique circuitry to control the voltage and drivers are enabled on alternate clock cycles. Internal current slew rates of the output switches. Slew control slope compensation is provided to ensure stability under capability provides much greater control over power sup- high duty cycle conditions. 6
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