Datasheet LT1533 (Analog Devices) - 9

LT1533
U U W U APPLICATIONS INFORMATION
slower slewing waveforms will dissipate more power so internal regulator voltage (2.4V typ), output regulation that efficiency will drop. You can also monitor this as you may be disrupted. A series resistance with the feedback make your slew adjustment by measuring input and out- pin can eliminate this potential problem. put voltage and current.
Negative Output Voltage Setting
It is possible to use a single slew setting resistor. In this case the R Negative output voltage can be sensed using the NFB pin. VSL and RCSL pins are tied together. A resistor with a value of 2k to 34k (one half the individual resistors) In this case regulation will occur when the NFB pin is at can then be tied from these pins to ground. – 2.5V. The input bias current for the NFB is –25µA (INFB) which needs to be accounted for in setting up the divider.
Emitter Inductance
Referring to Figure 2, R1 is chosen such that: A small inductance in the power ground minimizes a potential dip in the output current falling edge that can  V .  OUT − 2 5 occur under fast slewing, 25nH is usually sufficient. Greater R1= R2  than 50nH may produce unwanted oscillations in the 2 5 . + R2 • 25 A  µ  voltage output. The inductance can be created by wire or board trace with the equivalent of one inch of straight R1 length. A spiral board trace will require less length. NFB PIN –VOUT INFB R2
Positive Output Voltage Setting
1533 F02 Sensing of a positive output voltage is usually done using a resistor divider from the output to the FB pin. The
Figure 2
positive input to the error amp is connected internally to a 1.25V bandgap reference. The FB pin will regulate to this A suggested value for R2 is 2.5k. The NFB pin is normally voltage. left open if the FB pin is being used. R1 FB PIN V
Dual Polarity Output Voltage Sensing
OUT R2 Certain applications may benefit from sensing both posi- tive and negative output voltages. When doing this each 1533 F01 output voltage resistor divider is individually set as previ-
Figure 1
ously described. When both FB and NFB pins are used, the LT1533 will act to prevent either output from going Referring to Figure 1, R1 is determined by: beyond its set output voltage. The highest output (lightest load) will dominate control of the regulator. This technique  V  would prevent either output from going unregulated high R = R OUT 1 2 − 1  1 25  . at no load. However, this technique will also compromise output load regulation. The FB bias current represents a small error and can usually be ignored for values of R1|| R2 up to 10k.
Shutdown
One word of caution. Sometimes a feedback zero is added If the shutdown pin is pulled low, the regulator will turn off. to the control loop by placing a capacitor across R1 above. The supply current will be reduced to less than 20µA. If the feedback capacitively pulls the FB pin above the 9