Datasheet LT1931, LT1931A (Analog Devices) - 4

LT1931/LT1931A
W BLOCK DIAGRA
V V IN 5 IN R5 R6 80k 80k 1 SW + COMPARATOR – A1 g DRIVER m LATCH – A2 R Q Q3 RC RAMP + S Q1 Q2 Σ GENERATOR x10 CC + VOUT R3 0.01Ω 30k 1.2MHz – R1 CPL OSCILLATOR (EXTERNAL) R4 (OPTIONAL) 150k NFB SHDN 3 NFB 4 SHUTDOWN 2 GND R2 (EXTERNAL) 1931 BD
Figure 2 U OPERATIO
The LT1931 uses a constant frequency, current mode current level to keep the output in regulation. If the error control scheme to provide excellent line and load regula- amplifier’s output increases, more current is taken from tion. Operation can be best understood by referring to the the output; if it decreases, less current is taken. One Block Diagram in Figure 2. At the start of each oscillator function not shown in Figure 2 is the current limit. The cycle, the SR latch is set, turning on the power switch Q3. switch current is constantly monitored and not allowed to A voltage proportional to the switch current is added to a exceed the nominal value of 1.2A. If the switch current stabilizing ramp and the resulting sum is fed into the reaches 1.2A, the SR latch is reset regardless of the state positive terminal of the PWM comparator A2. When this of comparator A2. This current limit protects the power voltage exceeds the level at the negative input of A2, the SR switch as well as various external components connected latch is reset, turning off the power switch. The level at the to the LT1931. negative input of A2 is set by the error amplifier (gm) and The Block Diagram for the LT1931A is identical except that is simply an amplified version of the difference between the oscillator is 2.2MHz and resistors R3 to R6 are one-half the feedback voltage and the reference voltage of –1.255V. the LT1931 values. In this manner, the error amplifier sets the correct peak 1931fa 4