Datasheet LTC3772 (Analog Devices) - 6

LTC3772
U U U PI FU CTIO S (DDB/TS8) GND (Pin 1/Pin 4):
Ground Pin.
NC (Pin 5/Pin 8):
No Connection Required.
VFB (Pin 2/Pin 3):
Receives the feedback voltage from an
SW (Pin 6/Pin 7):
Switch Node Connection to Inductor external resistor divider across the output. and Current Sense Input Pin. Normally, the external P-channel MOSFET’s drain is connected to this pin.
ITH/RUN (Pin 3/Pin 2):
This pin performs two functions. It serves as the error amplifier compensation point as well as
VIN (Pin 7/Pin 6):
Supply and Current Sense Input Pin. the run control input. Nominal voltage range for this pin is This pin must be closely decoupled to GND (Pin 4). 0.7V to 1.9V. Forcing this pin below 0.6V causes the Normally the external P-channel MOSFET’s source is device to be shut down. In shutdown, all functions are connected to this pin. disabled and the PGATE pin is held high.
PGATE (Pin 8/Pin 5):
Gate Drive for the External P-Channel
IPRG (Pin 4/Pin 1):
Current Sense Limit Pin. Three-state MOSFET. This pin swings from 0V to VIN. pin selects maximum peak sense voltage threshold. The
Exposed Pad (Pin 9, DDB Only):
The Exposed Pad is pin selects the maximum voltage drop across the external ground and must be soldered to the PCB for electrical P-channel MOSFET. Tie to VIN, GND or float to select connection and optimum thermal performance. 245mV, 105mV or 175mV respectively. 3772f 6