Datasheet LT3517 (Analog Devices) - 6

LT3517
pin Functions SW:
Switch Pin. Minimize trace at this pin to reduce EMI.
CTRL:
LED Current Adjustment Pin. Sets voltage across
V
sense resistor between ISP and ISN. Connect directly to
IN:
Input Supply Pin. Must be locally bypassed. VREF for full-scale threshold of 100mV, or use signal values
SHDN:
Shutdown Pin. Tie to 1.5V or higher to enable between GND and 1V to modulate LED current. Tie the CTRL device or 0.4V or less to disable device. pin to the VREF pin if not used.
VREF:
Reference Output Pin. This pin can supply up to
VC:
gm Error Amplifier Output Pin. Stabilize the loop with 100µA. an RC network or compensating C.
RT :
Switching Frequency Adjustment Pin. Set switching
FB:
Voltage Loop Feedback Pin. Works as overvoltage frequency using a resistor to GND (see Typical Performance protection for LED drivers. If FB is higher than 1V, the Characteristics for values). For SYNC function, choose main switch is turned off. the resistor to program a frequency 20% slower than the SYNC pulse frequency. Do not leave this pin open.
TGEN:
Top Gate Enable Input Pin. Tie to 1.5V or higher to enable the PMOS driver function. Tie the TGEN pin to
SYNC:
Frequency Synchronization Pin. Tie an external ground if TG function is not used. There is an equivalent clock signal here. RT resistor should be chosen to pro- 40k resistor from TGEN pin to ground internally. gram a switching frequency 20% slower than SYNC pulse frequency. Synchronization (power switch turn-on) occurs
ISN:
Current Sense (–) Pin. The inverting input to the a fixed delay after the rising edge of SYNC. Tie the SYNC current sense amplifier. pin to ground if this feature is not used.
ISP:
Current Sense (+) Pin. The noninverting input to the
SS:
Soft-Start Pin. Place a soft-start capacitor here. Leave current sense amplifier. Also serves as positive rail for the pin open if not in use. TG pin driver.
PWM:
Pulse Width Modulated Input Pin. Signal low turns
TG:
Top Gate Driver Output. An inverted PWM sig- off channel, disables the main switch and makes the TG nal drives series PMOS device between VISP and pin high. Tie the PWM pin to V (V REF pin or SHDN pin if not ISP – 7V). An internal 7V clamp protects the PMOS gate. used. There is an equivalent 50k resistor from PWM pin Leave TG unconnected if not used. to ground internally.
GND:
Exposed Pad (QFN Package). Solder paddle directly to ground plane. 3517fh 6 For more information www.linear.com/LT3517 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Related Parts