Datasheet AD4000, AD4004 (Analog Devices)

ПроизводительAnalog Devices
Описание16-Bit, 2 MSPS/1 MSPS, Precision, Pseudo Differential, SAR ADCs
Страниц / Страница34 / 1 — 16-Bit, 2 MSPS/1 MSPS, Precision,. Pseudo Differential, SAR ADCs. Data …
ВерсияA
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Язык документаанглийский

16-Bit, 2 MSPS/1 MSPS, Precision,. Pseudo Differential, SAR ADCs. Data Sheet. AD4000. /AD4004. FEATURES. GENERAL DESCRIPTION

Datasheet AD4000, AD4004 Analog Devices, Версия: A

Текстовая версия документа

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16-Bit, 2 MSPS/1 MSPS, Precision, Pseudo Differential, SAR ADCs Data Sheet AD4000 /AD4004 FEATURES GENERAL DESCRIPTION Throughput: 2 MSPS/1 MSPS options
The AD4000/AD4004 are low noise, low power, high speed, 16-bit,
INL: ±1.0 LSB maximum
precision successive approximation register (SAR) analog-to-digital
Guaranteed 16-bit, no missing codes
converters (ADCs). The AD4000 offers a 2 MSPS throughput, and
Low power
the AD4004 offers a 1 MSPS throughput. They incorporate ease of
9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS (VDD only)
use features that lower the signal chain power, reduce signal chain
70 µW at 10 kSPS, 14 mW at 2 MSPS (total)
complexity, and enable higher channel density. The high-Z mode,
SNR: 93 dB typical at 1 kHz, VREF = 5 V; 90 dB typical at 100 kHz
coupled with a long acquisition phase, eliminates the need for a
THD: −115 dB typical at 1 kHz, VREF = 5 V; −95 dB typical at 100 kHz
dedicated high power, high speed ADC driver, thus broadening the
Ease of use features reduce system power and complexity
range of low power precision amplifiers that can drive these ADCs
Input overvoltage clamp circuit
directly while still achieving optimum performance. The input
Reduced nonlinear input charge kickback
span compression feature enables the ADC driver amplifier and the
High-Z mode
ADC to operate off common supply rails without the need for a
Long acquisition phase
negative supply while preserving the full ADC code range. The
Input span compression
low serial peripheral interface (SPI) clock rate requirement reduces
Fast conversion time allows low SPI clock rates
the digital input/output power consumption, broadens processor
SPI-programmable modes, read/write capability, status word
options, and simplifies the task of sending data across digital
Pseudo differential (single-ended) analog input range
isolation.
0 V to VREF with VREF from 2.4 V to 5.1 V Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
Operating from a 1.8 V supply, the AD4000/AD4004 sample an
SAR architecture: no latency/pipeline delay, valid first conversion
analog input (IN+) from 0 V to VREF with respect to a ground sense
First accurate conversion
(IN−) with VREF ranging from 2.4 V to 5.1 V. The AD4000
Guaranteed operation: −40°C to 125°C
consumes only 14 mW at 2 MSPS with a minimum of 70 MHz
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
SCK rate in turbo mode. The AD4004 consumes only 7 mW at
Ability to daisy-chain multiple ADCs and busy indicator
1 MSPS with a minimum of 25 MHz SCK rate in turbo mode. Both
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
the AD4000/AD4004 achieve ±1.0 LSB integral nonlinearity error (INL) maximum, no missing codes at 16 bits, and 93 dB signal-to-
APPLICATIONS
noise ratio (SNR). The reference voltage is applied externally and
Automatic test equipment
can be set independently of the supply voltage.
Machine automation Medical equipment
The SPI-compatible versatile serial interface features seven
Battery-powered equipment
different modes including the ability, using the SDI input, to
Precision data acquisition systems
daisy-chain several ADCs on a single 3-wire bus, and provides an

optional busy indicator. The AD4000/AD4004 are compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. The AD4000/AD4004 are available in a 10-lead MSOP or LFCSP with operation specified from −40°C to +125°C. The devices are pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8).
FUNCTIONAL BLOCK DIAGRAM 2.4V TO 5.1V 1.8V 10µF REF VDD VIO VREF HIGH-Z AD4000/ 1.8V TO 5V V TURBO REF/2 SDI MODE AD4004 MODE 0 IN+ SCK 16-BIT SERIAL 3-WIRE OR 4-WIRE SAR ADC INTERFACE SDO SPI INTERFACE (DAISY CHAIN, CS) IN– STATUS CNV CLAMP SPAN COMPRESSON BITS
001
GND
14956- Figure 1.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION TRANSFER FUNCTIONS APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS ANALOG INPUTS Input Overvoltage Clamp Circuit Switched Capacitor Input RC Filter Values DRIVER AMPLIFIER CHOICE High Frequency Input Signals EASE OF DRIVE FEATURES Input Span Compression High-Z Mode Long Acquisition Phase VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE REGISTER READ/WRITE FUNCTIONALITY STATUS WORD CSB MODE, 3-WIRE TURBO MODE CSB MODE, 3-WIRE WITHOUT BUSY INDICATOR CSB MODE, 3-WIRE WITH BUSY INDICATOR CSB MODE, 4-WIRE TURBO MODE CSB MODE, 4-WIRE WITHOUT BUSY INDICATOR CSB MODE, 4-WIRE WITH BUSY INDICATOR DAISY-CHAIN MODE LAYOUT GUIDELINES EVALUATING THE AD4000/AD4004 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE