link to page 1 link to page 1 link to page 1 link to page 3 link to page 4 link to page 4 link to page 5 link to page 5 link to page 6 link to page 8 link to page 9 link to page 10 link to page 12 link to page 12 link to page 12 link to page 13 link to page 15 link to page 22 link to page 24 link to page 24 link to page 24 link to page 25 link to page 26 link to page 26 link to page 29 link to page 29 link to page 29 link to page 30 link to page 30 link to page 33 link to page 33 link to page 33 link to page 33 link to page 39 link to page 39 link to page 40 link to page 40 link to page 42 link to page 42 link to page 43 link to page 44 link to page 44 link to page 45 link to page 50 link to page 50 link to page 50 link to page 52 link to page 52 link to page 53 link to page 54 link to page 56 link to page 60 link to page 60 link to page 61 link to page 63 link to page 65 link to page 65 link to page 66 link to page 68 link to page 68 link to page 68 link to page 68 link to page 69 link to page 69 link to page 70 link to page 70 link to page 76 link to page 101 link to page 101 link to page 101 link to page 101 link to page 102 link to page 102 AD9694Data SheetTABLE OF CONTENTS \Features ... 1 FIR Filters .. 41 Applications .. 1 Overview ... 41 Functional Block Diagram ... 1 Half-Band Filters .. 42 Revision History ... 2 DDC Gain Stage ... 43 General Description .. 3 DDC Complex to Real Conversion ... 43 Product Highlights .. 3 DDC Example Configurations ... 44 Specifications .. 4 Digital Outputs ... 49 DC Specifications .. 4 Introduction to the JESD204B Interface ... 49 AC Specifications ... 5 Setting Up the AD9694 Digital Interface .. 49 Digital Specifications .. 7 Functional Overview ... 51 Switching Specifications ... 8 JESD204B Link Establishment ... 51 Timing Specifications ... 9 Physical Layer (Driver) Outputs .. 52 Absolute Maximum Ratings .. 11 JESD204B Tx Converter Mapping ... 53 Thermal Resistance ... 11 Configuring the JESD204B Link .. 55 ESD Caution ... 11 Latency ... 59 Pin Configuration and Function Descriptions .. 12 End-to-End Total Latency ... 59 Typical Performance Characteristics.. 14 Multichip Synchronization .. 60 Equivalent Circuits .. 21 SYSREF± Set up and Hold Window Monitor .. 62 Theory of Operation ... 23 Test Modes ... 64 ADC Architecture ... 23 ADC Test Modes .. 64 Analog Input Considerations .. 23 JESD204B Block Test Modes .. 65 Voltage Reference .. 24 Serial Port Interface .. 67 DC Offset Calibration .. 25 Configuration Using the SPI ... 67 Clock Input Considerations .. 25 Hardware Interface ... 67 ADC Overrange and Fast Detect .. 28 SPI Accessible Features .. 67 ADC Overrange... 28 Memory Map .. 68 Fast Threshold Detection (FD_A, FD_B, FD_C, and FD_D) .. 28 Reading the Memory Map Register Table ... 68 Signal Monitor .. 29 Memory Map .. 69 SPORT Over JESD204B ... 29 Register Table Summary .. 69 Digital Downconverter (DDC) ... 32 Memory Map Register Table—Details .. 75 DDC I/Q Input Selection .. 32 Applications Information .. 100 DDC I/Q Output Selection ... 32 Power Supply Recommendations ... 100 DDC General Description .. 32 Exposed Pad Thermal Heat Slug Recommendations .. 100 Frequency Translation ... 38 AVDD1_SR (Pin 64) and AGND_SR (Pin 63 and Pin 67) ... 100 General Description ... 38 Outline Dimensions ... 101 DDC NCO and Mixer Loss and SFDR .. 39 Ordering Guide .. 101 Numerically Controlled Oscillator ... 39 REVISION HISTORY10/2016—Revision 0: Initial Version Rev. 0 | Page 2 of 101 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Dither Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A, FD_B, FD_C, AND FD_D) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO AND MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS OVERVIEW HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE SETTING UP THE AD9694 DIGITAL INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) JESD204B Tx CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs in Each Pair) LATENCY END-TO-END TOTAL LATENCY MULTICHIP SYNCHRONIZATION SYSREF± SET UP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels ADC Pair Addressing Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE SUMMARY MEMORY MAP REGISTER TABLE—DETAILS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 64) AND AGND_SR (PIN 63 AND PIN 67) OUTLINE DIMENSIONS ORDERING GUIDE
