Datasheet AD7124-8 (Analog Devices)

8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Data Sheet AD7124-8 FEATURES Low-side power switch 3 power modes General-purpose outputs RMS noise Multiple filter options Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical) Internal temperature sensor Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical) Self and system calibration Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical) Sensor burnout detection Up to 22 noise free bits in all power modes (gain = 1) Automatic channel sequencer Output data rate Per channel configuration Full power: 9.38 SPS to 19,200 SPS Power supply: 2.7 V to 3.6 V and ±1.8 V Mid power: 2.34 SPS to 4800 SPS Independent interface power supply Low power: 1.17 SPS to 2400 SPS Power-down current: 5 µA maximum Rail-to-rail analog inputs for gains > 1 Temperature range: −40°C to +125°C Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle 32-lead LFCSP settling) 3-wire or 4-wire serial interface Diagnostic functions (which aid safe integrity level (SIL) SPI, QSPI™, MICROWIRE™, and DSP compatible certification) Schmitt trigger on SCLK Crosspoint multiplexed analog inputs ESD: 4 kV 8 differential/15 pseudo differential inputs APPLICATIONS Programmable gain (1 to 128) Temperature measurement Band gap reference with 15 ppm/°C drift maximum (70 µA) Pressure measurement Matched programmable excitation currents Industrial process control Internal clock oscillator Instrumentation On-chip bias voltage generator Smart transmitters FUNCTIONAL BLOCK DIAGRAM AV REGCAPA IOV DD REFOUT REFIN1(+) REFIN1(–) DD REGCAPD V BANDGAP BIAS REFIN2(+) 1.9V AV REF DD AVSS 1.8V AV REFIN2(–) LDO LDO CROSSPOINT SS MUX AIN0/IOUT/VBIAS AVDD AIN1/IOUT/VBIAS REFERENCE AIN2/IOUT/VBIAS/P1 BUFFERS AIN3/IOUT/VBIAS/P2 DOUT/RDY AIN4/IOUT/VBIAS/P3 BUF SERIAL AIN5/IOUT/VBIAS/P4 24-BIT VARIABLE BURNOUT INTERFACE PGA1 PGA2 DIN AIN6/IOUT/VBIAS DETECT Σ-Δ ADC DIGITAL AND FILTER AIN7/IOUT/VBIAS BUF CONTROL SCLK LOGIC AIN8/IOUT/VBIAS X-MUX CS AIN9/IOUT/VBIAS AIN10/IOUT/VBIAS ANALOG AVSS CHANNEL BUFFERS AIN11/IOUT/VBIAS SEQUENCER AIN12/IOUT/VBIAS SYNC AIN13/IOUT/VBIAS AIN14/IOUT/VBIAS/REFIN2(+) GPOs DIAGNOSTICS AIN15/IOUT/VBIAS/REFIN2(–) TEMPERATURE AVDD COMMUNICATIONS SENSOR INTERNAL POWER SUPPLY CLOCK CLK SIGNAL CHAIN DIAGNOSTICS EXCITATION DIGITAL PSW CURRENTS POWER SWITCH AD7124-8 AVSS
001
AVSS DGND
13048- Figure 1.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION FULL POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) MID POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) LOW POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) GETTING STARTED OVERVIEW Power Modes Analog Inputs Multiplexer Reference Programmable Gain Array (PGA) Burnout Currents Σ-Δ ADC and Filter Channel Sequencer Per Channel Configuration Serial Interface Clock Temperature Sensor Digital Outputs Calibration Excitation Currents Bias Voltage Bridge Power Switch (PSW) Diagnostics POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Configuration Registers Filter Registers Offset Registers Gain Registers Diagnostics ADC Control Register Understanding Configuration Flexibility ADC CIRCUIT INFORMATION ANALOG INPUT CHANNEL EXTERNAL IMPEDANCE WHEN USING A GAIN OF 1 PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING EXCITATION CURRENTS BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS BIAS VOLTAGE GENERATOR CLOCK POWER MODES STANDBY AND POWER-DOWN MODES DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode DATA_STATUS SERIAL INTERFACE RESET (DOUT__DEL AND _EN BITS) RESET CALIBRATION SPAN AND OFFSET LIMITS SYSTEM SYNCHRONIZATION DIGITAL FILTER SINC4 FILTER Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sequencer Sinc4 50 Hz and 60 Hz Rejection SINC3 FILTER Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sequencer Sinc3 50 Hz and 60 Hz Rejection FAST SETTLING MODE (SINC4 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc4 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc4 + Sinc1 Filter FAST SETTLING MODE (SINC3 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc3 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc3 + Sinc1 Filter POST FILTERS SUMMARY OF FILTER OPTIONS DIAGNOSTICS SIGNAL CHAIN CHECK REFERENCE DETECT CALIBRATION, CONVERSION, AND SATURATION ERRORS OVERVOLTAGE/UNDERVOLTAGE DETECTION POWER SUPPLY MONITORS LDO MONITORING Power Supply Monitor LDO Capacitor Detect MCLK COUNTER SPI SCLK COUNTER SPI READ/WRITE ERRORS SPI_IGNORE ERROR CHECKSUM PROTECTION MEMORY MAP CHECKSUM PROTECTION ROM CHECKSUM PROTECTION CRC Calculation Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) BURNOUT CURRENTS TEMPERATURE SENSOR GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE MEASUREMENT USING A THERMOCOUPLE TEMPERATURE MEASUREMENT USING AN RTD FLOWMETER ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER ADC_CONTROL REGISTER DATA REGISTER IO_CONTROL_1 REGISTER IO_CONTROL_2 REGISTER ID REGISTER ERROR REGISTER ERROR_EN REGISTER MCLK_COUNT REGISTER CHANNEL REGISTERS CONFIGURATION REGISTERS FILTER REGISTERS OFFSET REGISTERS GAIN REGISTERS OUTLINE DIMENSIONS ORDERING GUIDE