Datasheet AD9655 (Analog Devices) - 10

Data Sheet AD9655 Timing Diagrams N – 1 VINx± N t N + 1 A tEH tEL CLK– CLK+ tCPD DCO– DDR DCO+ DCO– SDR DCO+ tFCO tFRAME FCO– FCO+ t t D0A– PD DATA BITWISE D14 D12 D10 D08 D06 D04 D02 LSB D14 D12 D10 D08 D06 D04 D02 LSB MODE D0A+ N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1A– MSB D13 D11 D09 D07 D05 D03 D01 MSB D13 D11 D09 D07 D05 D03 D01 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1A+ FCO– FCO+ D0A– BYTEWISE D07 D06 D05 D04 D03 D2 D01 LSB D07 D06 D05 D04 D03 D02 D01 LSB MODE N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D0A+ D1A– MSB D14 D13 D12 D11 D10 D09 D08 MSB D14 D13 D12 D11 D10 D09 D08
002
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1A+
12737- Figure 2. 16-Bit DDR/Single Data Rate (SDR), Two-Lane, 1× Frame Mode (Default)
N – 1 VINx± tA N tEH tEL CLK– CLK+ tCPD DCO– DCO+ tFCO tFRAME FCO– FCO+ t tDATA PD D0x– MSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB MSB D14 D13 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16
003
D0x+
12737- Figure 3. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode Rev. 0 | Page 9 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.4 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—0 Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—000 Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—Disable SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—000 Clock Monitor Control (Register 0x112) Bit 7—Open Bit 6—0 (Reserved) Bits[5:3]—Recovery Mode Bits[2:0]— Recovery Mode Setup VREF Control (Register 0x114) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE BYPASSING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE