ADAS3023* PRODUCT PAGE QUICK LINKS Last Content Update: 06/09/2017COMPARABLE PARTSREFERENCE MATERIALS View a parametric search of comparable parts. Technical Articles • Exploring Different SAR ADC Analog Input Architectures EVALUATION KITS • Let's Compare SAR & Δ-Σ Converters for a Mux'd DAS • ADAS3023 Evaluation Kit (Planet Analog, 12/2013) DOCUMENTATIONDESIGN RESOURCESData Sheet • ADAS3023 Material Declaration • ADAS3023: 16-Bit, 8-Channel Simultaneous Sampling • PCN-PDN Information Data Acquisition System Data Sheet • Quality And Reliability User Guides • Symbols and Footprints • UG-515: Evaluation Board for the ADAS3023 16-Bit, 8- Channel, Simultaneous Sampling Data Acquisition System DISCUSSIONS View all ADAS3023 EngineerZone Discussions. TOOLS AND SIMULATIONS • ADAS3023 FPGA Reference Design SAMPLE AND BUY • ADAS3022/ADAS3023 IBIS Model Visit the product page to see pricing options. REFERENCE DESIGNSTECHNICAL SUPPORT • CN0201 Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified. Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Circuit and Voltage Diagrams Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Operation Transfer Functions Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Voltage Reference Input/Output Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising--Start of Conversion (SOC) BUSY/SDO2 Falling Edge—End of Conversion (EOC) Register Pipeline RESET and Power-Down (PD) Inputs Serial Data Interface General Timing Configuration Register Packaging and Ordering Information Outline Dimensions Ordering Guide
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