Datasheet ADAS3023 (Analog Devices) - 8

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Data Sheet ADAS3023 Parameter Symbol Min Typ Max Unit
DIN DIN Valid Setup Time from SCK Falling Edge tDINS 4 ns DIN Valid Hold Time from SCK Falling Edge tDINH 4 ns RESET/PD HIGH PULSE tRH 5 ns 1 See Figure 2 and Figure 3 for load conditions. 2 Exceeding the maximum time has an effect on the accuracy of the conversion (see the Conversion Modes section).
Circuit and Voltage Diagrams 500µA IOL TO SDO 1.4V CL 50pF
002
500µA IOH
10942- Figure 2. Load Circuit for Digital Interface Timing
70% VIO 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2
003
12V IF VIO > 2.5V; VIO – 0.5V IF VIO < 2.5V. 20.8V IF VIO > 2.5V; 0.5V IF VIO < 2.5V.
10942- Figure 3. Voltage Levels for Timing Rev. A | Page 7 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Circuit and Voltage Diagrams Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Operation Transfer Functions Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Voltage Reference Input/Output Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising--Start of Conversion (SOC) BUSY/SDO2 Falling Edge—End of Conversion (EOC) Register Pipeline RESET and Power-Down (PD) Inputs Serial Data Interface General Timing Configuration Register Packaging and Ordering Information Outline Dimensions Ordering Guide